Note:
This technique can result in a priority inversion.
•
Ensure that each ISR saves and restores registers on entry and exit, and set
status.RSIE
to 1 after registers are saved. When an ISR is running in a given
register set, the processor takes an interrupt in the same register set if it has a
higher interrupt level.
The Nios II processor disables interrupts when taking a maskable interrupt
(nonmaskable interrupts always disable maskable interrupts). Individual ISRs can re-
enable nested interrupts by setting
status.PIE
to 1, as described in the Nested
"Exceptions with Internal Interrupt Controller" section of this chapter.
Related Information
Nested Exceptions with the Internal Interrupt Controller
on page 94
3.7.12. Handling Nonmaskable Interrupts
Writing an NMI handler involves the same basic techniques as writing any other
interrupt handler. However, nonmaskable interrupts always preempt maskable
interrupts, and cannot be preempted. This knowledge can simplify handler design in
some ways, but it means that an NMI handler can have a significant impact on overall
interrupt latency. For the best system performance, perform the absolute minimum of
processing in your NMI handlers, and defer less-critical processing to maskable
interrupt handlers or foreground software.
NMIs leave intact the processor state associated with maskable interrupts and other
exceptions, as well as normal, nonexception processing, when each NMI is assigned to
a dedicated shadow register set. Therefore, NMIs can be handled transparently.
Note:
If not assigned to a dedicated shadow register set, an NMI can overwrite the
processor status associated with exception processing, making it impossible to return
to the interrupted exception.
Note:
Do not set
status.PIE
in a nonmaskable ISR. If
status.PIE
is set, a maskable
interrupt can pre-empt an NMI, and the processor exits NMI mode. It cannot be
returned to NMI mode until the next nonmaskable interrupt.
3.7.13. Masking and Disabling Exceptions
The Nios II processor provides several methods for temporarily turning off some or all
exceptions from software. The available methods depend on the hardware
configuration. This section discusses all potentially available methods.
3.7.13.1. Disabling Maskable Interrupts
Software can disable and enable maskable interrupts with the
status.PIE
bit. When
PIE
= 0, maskable interrupts are ignored. When
PIE
= 1, internal and maskable
external interrupts can be taken, depending on the status of the interrupt controller.
3.7.13.2. Masking Interrupts with an External Interrupt Controller
Typical EIC implementations allow system software to mask individual interrupts. The
method of masking individual interrupts is implementation-specific.
3. Programming Model
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Nios II Processor Reference Guide
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