The Nios II instruction set provides several different instructions to clear the data
cache. There are two important questions to answer when determining the instruction
to use. Do you need to consider the tag field when looking for a cache match? Do you
need to write dirty cache lines back to memory before clearing? Below the table lists
the most appropriate instruction to use for each case.
Table 66.
Data Cache Clearing Instructions
Instruction
Ignore Tag Field
Consider Tag Field
Write Dirty Lines
flushd
flushda
Do Not Write Dirty Lines
initd
initda
For more information regarding the Nios II instruction set, refer to the Instruction Set
Reference chapter of the Nios II Processor Reference Handbook.
The Nios II/f core implements all the data cache bypass methods.
For information regarding the data cache bypass methods, refer to the Processor
Architecture chapter of the Nios II Processor Reference Handbook
Mixing cached and uncached accesses to the same cache line can result in invalid data
reads. For example, the following sequence of events causes cache incoherency.
1. The Nios II core writes data to cache, creating a dirty data cache line.
2. The Nios II core reads data from the same address, but bypasses the cache.
Note:
Avoid mixing cached and uncached accesses to the same cache line, regardless
whether you are reading from or writing to the cache line. If it is necessary to mix
cached and uncached data accesses, flush the corresponding line of the data cache
after completing the cached accesses and before performing the uncached accesses.
Related Information
•
Instruction Set Reference
on page 169
•
Processor Architecture
on page 14
5.2.3.2.3. Bursting
When the data cache is enabled, you can enable bursting on the data master port.
Consult the documentation for memory devices connected to the data master port to
determine whether bursting can improve performance.
5.2.4. Tightly-Coupled Memory
The Nios II/f core provides optional tightly-coupled memory interfaces for both
instructions and data. A Nios II/f core can use up to four each of instruction and data
tightly-coupled memories. When a tightly-coupled memory interface is enabled, the
Nios II core includes an additional memory interface master port. Each tightly-coupled
memory interface must connect directly to exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes addresses
internally to determine if requested instructions or data reside in tightly-coupled
memory. If the address resides in tightly-coupled memory, the Nios II core fetches the
5. Nios II Core Implementation Details
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