The size of the tag field depends on the size of the cache memory and the physical
address size. The size of the line field depends only on the size of the cache memory.
The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte
address size is 31 bits.
The instruction cache is optional. However, excluding instruction cache from the
Nios II/s core requires that the core include at least one tightly-coupled instruction
memory.
5.3.4. Tightly-Coupled Memory
The Nios II/s core provides optional tightly-coupled memory interfaces for
instructions. A Nios II/s core can use up to four tightly-coupled instruction memories.
When a tightly-coupled memory interface is enabled, the Nios II core includes an
additional memory interface master port. Each tightly-coupled memory interface must
connect directly to exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes addresses
internally to determine if requested instructions reside in tightly-coupled memory. If
the address resides in tightly-coupled memory, the Nios II core fetches the instruction
through the tightly-coupled memory interface. Software does not require awareness of
whether code resides in tightly-coupled memory or not.
Accessing tightly-coupled memory bypasses cache memory. The processor core
functions as if cache were not present for the address span of the tightly-coupled
memory. Instructions for managing cache, such as
initi
and
flushi
, do not affect
the tightly-coupled memory, even if the instruction specifies an address in tightly-
coupled memory.
5.3.5. Execution Pipeline
This section provides an overview of the pipeline behavior for the benefit of
performance-critical applications. Designers can use this information to minimize
unnecessary processor stalling. Most application programmers never need to analyze
the performance of individual instructions.
The Nios II/s core employs a 5-stage pipeline.
Table 73.
Implementation Pipeline Stages for Nios II/s Core
Stage Letter
Stage Name
F
Fetch
D
Decode
E
Execute
M
Memory
W
Writeback
5. Nios II Core Implementation Details
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