Exceptions
Misaligned destination address
Supervisor-only instruction
Instruction Type
R
Instruction Fields
None
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0x1d
0x1e
C
0x01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x01
0
0x3a
8.5.45. flushd
Instruction
flush data cache line
Operation
Flushes the data cache line associated with address
rA + σ(IMM16).
Assembler Syntax
flushd IMM16(rA)
Example
flushd -100(r6)
Description
If the Nios II processor implements a direct mapped data
cache,
flushd
writes the data cache line that is mapped to
the specified address back to memory if the line is dirty, and
then clears the data cache line. Unlike
flushda
,
flushd
writes the dirty data back to memory even when the
addressed data is not currently in the cache. This process
comprises the following steps:
• Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
• Identify the data cache line associated with the
computed effective address. Each data cache effective
address comprises a
tag
field and a
line
field. When
identifying the data cache line,
flushd
ignores the
tag
field and only uses the
line
field to select the data
cache line to clear.
• Skip comparing the cache line tag with the effective
address to determine if the addressed data is currently
cached. Because
flushd
ignores the cache line tag,
flushd
flushes the cache line regardless of whether the
specified data location is currently cached.
• If the data cache line is dirty, write the line back to
memory. A cache line is dirty when one or more words of
the cache line have been modified by the processor, but
are not yet written to memory.
• Clear the valid bit for the line.
If the Nios II processor core does not have a data cache,
the
flushd
instruction performs no operation.
Usage
Use
flushd
to write dirty lines back to memory even if the
addressed memory location is not in the cache, and then
flush the cache line. By contrast, refer to “flushda flush data
cache address”, “initd initialize data cache line”, and “initda
initialize data cache address” for other cache-clearing
options.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
continued...
8. Instruction Set Reference
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
198
