5.2.7. Execution Pipeline
This section provides an overview of the pipeline behavior for the benefit of
performance-critical applications. Designers can use this information to minimize
unnecessary processor stalling. Most application programmers never need to analyze
the performance of individual instructions.
The Nios II/f core employs a 6-stage pipeline.
Table 67.
Implementation Pipeline Stages for Nios II/f Core
Stage Letter
Stage Name
F
Fetch
D
Decode
E
Execute
M
Memory
A
Align
W
Writeback
Up to one instruction is dispatched and/or retired per cycle. Instructions are
dispatched and retired in order. Dynamic branch prediction is implemented using a 2-
bit branch history table. The pipeline stalls for the following conditions:
•
Multicycle instructions
•
Avalon-MM instruction master port read accesses
•
Avalon-MM data master port read/write accesses
•
Data dependencies on long latency instructions (e.g., load, multiply, shift).
5.2.7.1. Pipeline Stalls
The pipeline is set up so that if a stage stalls, no new values enter that stage or any
earlier stages. No “catching up” of pipeline stages is allowed, even if a pipeline stage
is empty.
Only the A-stage and D-stage are allowed to create stalls.
The A-stage stall occurs if any of the following conditions occurs:
•
An A-stage memory instruction is waiting for Avalon-MM data master requests to
complete. Typically this happens when a load or store misses in the data cache, or
a
flushd
instruction needs to write back a dirty line.
•
An A-stage shift/rotate instruction is still performing its operation. This only occurs
with the multicycle shift circuitry (i.e., when the hardware multiplier is not
available).
•
An A-stage divide instruction is still performing its operation. This only occurs
when the optional divide circuitry is available.
•
An A-stage multicycle custom instruction is asserting its stall signal. This only
occurs if the design includes multicycle custom instructions.
5. Nios II Core Implementation Details
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