Table 10.
TLB Data Portion Contents
Field Name
Description
PFN
PFN
is the physical frame number field. This field specifies the upper bits of the physical address.
The size of this field depends on the range of physical addresses present in the system. The
maximum size is 20 bits.
C
C
is the cacheable flag. Determines the default data cacheability of a page. Can be overridden for
data accesses using I/O load and store family of Nios II instructions.
R
R
is the readable flag. Allows load instructions to read a page.
W
W
is the writable flag. Allows store instructions to write a page.
X
X
is the executable flag. Allows instruction fetches from a page.
Note:
Because there is no “valid bit” in the TLB entry, the operating system software
invalidates the TLB by writing unique VPN values from the I/O partition of virtual
addresses into each TLB entry.
Related Information
•
Programming Model
on page 36
•
Nios II Core Implementation Details
on page 121
3.2.5. TLB Lookups
A TLB lookup attempts to convert a virtual address (VADDR) to a physical address
(PADDR).
Example 1. TLB Lookup Algorithm for Instruction Fetches
if (VPN match && (G == 1 || PID match))
if (X == 1)
PADDR = concat(PFN, VADDR[11:0])
else take TLB permission violation exception
else
if (EH bit of status register == 1)
take double TLB miss exception
else
take fast TLB miss exception
Example 2. TLB Lookup Algorithm for Data Access Operations
if (VPN match && (G == 1 || PID match))
if ((load && R == 1) || (store && W == 1) || flushda)
PADDR = concatenate(PFN, VADDR[11:0])
else
take TLB permission violation exception
else
if (EH bit of status register == 1)
take double TLB miss exception
else
take fast TLB miss exception
Refer to “Instruction-Related Exceptions” for information about TLB exceptions.
Related Information
Instruction-Related Exceptions
on page 83
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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