Register
Name
Register Contents
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
4
ipending
Pending internal interrupt bits
The ipending Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
5
cpuid
Unique processor identifier
6
Reserved
Reserved
7
exception
Refer to
The exception Register
8
pteaddr
Refer to
The pteaddr Register
Available only when the MMU is present. Otherwise
reserved.
9
tlbacc
Refer to
The tlbacc Register
Available only when the MMU is present. Otherwise
reserved.
10
tlbmisc
Refer to
The tlbmisc Register
Available only when the MMU is present. Otherwise
reserved.
11
eccinj
Refer to
The eccinj Register
Available only when ECC is present.
12
badaddr
Refer to
The badaddr Register
13
config
Refer to
The config Register
on page 58
Available only when the MPU or ECC is present.
Otherwise reserved.
14
mpubase
Refer to
The mpubase Register
Available only when the MPU is present. Otherwise
reserved.
15
mpuacc
Refer to
The mpuacc Register
for MASK variations table.
Available only when the MPU is present. Otherwise
reserved.
16–31
Reserved
Reserved
The following sections describe the nonreserved control registers.
Control registers report the status and change the behavior of the processor. Control
registers are accessed differently than the general-purpose registers. The special
instructions
rdctl
and
wrctl
provide the only means to read and write to the control
registers and are only available in supervisor mode.
Note:
When writing to control registers, all undefined bits must be written as zero.
The Nios II architecture supports up to 32 control registers. All nonreserved control
registers have names recognized by the assembler.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
47
