2.6.1.1. Memory and Peripheral Access
The Nios II architecture provides memory-mapped I/O access. Both data memory and
peripherals are mapped into the address space of the data master port. The Nios II
architecture uses little-endian byte ordering. Words and halfwords are stored in
memory with the more-significant bytes at higher addresses.
The Nios II architecture does not specify anything about the existence of memory and
peripherals; the quantity, type, and connection of memory and peripherals are
system-dependent. Typically, Nios II processor systems contain a mix of fast on-chip
memory and slower off-chip memory. Peripherals typically reside on-chip, although
interfaces to off-chip peripherals also exist.
2.6.1.2. Instruction Master Port
The Nios II instruction bus is implemented as a 32-bit Avalon-MM master port. The
instruction master port performs a single function: it fetches instructions to be
executed by the processor. The instruction master port does not perform any write
operations.
The instruction master port is a pipelined Avalon-MM master port. Support for
pipelined Avalon-MM transfers minimizes the impact of synchronous memory with
pipeline latency and increases the overall f
MAX
of the system. The instruction master
port can issue successive read requests before data has returned from prior requests.
The Nios II processor can prefetch sequential instructions and perform branch
prediction to keep the instruction pipe as active as possible.
The instruction master port always retrieves 32 bits of data. The instruction master
port relies on dynamic bus-sizing logic contained in the system interconnect fabric. By
virtue of dynamic bus sizing, every instruction fetch returns a full instruction word,
regardless of the width of the target memory. Consequently, programs do not need to
be aware of the widths of memory in the Nios II processor system.
The Nios II architecture supports on-chip cache memory for improving average
instruction fetch performance when accessing slower memory. Refer to the "Cache
Memory" section of this chapter for details.
The Nios II architecture supports tightly-coupled memory, which provides guaranteed
low-latency access to on-chip memory. Refer to the "Tightly-Coupled Memory" section
of this chapter for details.
Related Information
•
Cache Memory
on page 27
•
Tightly-Coupled Memory
on page 29
2.6.1.3. Data Master Port
The Nios II data bus is implemented as a 32-bit Avalon-MM master port. The data
master port performs two functions:
•
Read data from memory or a peripheral when the processor executes a load
instruction
•
Write data to memory or a peripheral when the processor executes a store
instruction
2. Processor Architecture
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Nios II Processor Reference Guide
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