Intel NIOS II, Owner Reference Manual

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Bit Description Access Reset Available
IH IH
is the interrupt handler mode bit. The processor sets
IH
to one
when it takes an external interrupt.
Read/Write 0 EIC interface only
( 9 )
EH
( 8 )
EH
is the exception handler mode bit. The processor sets
EH
to one
when an exception occurs (including breaks). Software clears
EH
to
zero when ready to handle exceptions again.
EH
is used by the MMU
to determine whether a TLB miss exception is a fast TLB miss or a
double TLB miss. In systems without an MMU,
EH
is always zero.
Read/Write 0 MMU or ECC only
( 9 )
U
( 8 )
U
is the user mode bit. When
U
= 1, the processor operates in user
mode. When
U
= 0, the processor operates in supervisor mode. In
systems without an MMU,
U
is always zero.
Read/Write 0 MMU or MPU only
( 9 )
PIE PIE
is the processor interrupt-enable bit. When
PIE
= 0, internal and
maskable external interrupts and noninterrupt exceptions are ignored.
When
PIE
= 1, internal and maskable external interrupts can be
taken, depending on the status of the interrupt controller.
Noninterrupt exceptions are unaffected by
PIE
.
Read/Write 0 Always
Related Information
External Interrupt Controller Interface
on page 80
3.4.2.2. The estatus Register
The
estatus
register holds a saved copy of the
status
register during nonbreak
exception processing.
Table 16. estatus Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved RSIE NMI PRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRS IL IH EH U PIE
All fields in the
estatus
register have read/write access. All fields reset to 0.
When the Nios II processor takes an interrupt, if
status.eh
is zero (that is, the MMU
is in nonexception mode), the processor copies the contents of the
status
register to
estatus
.
Note: If shadow register sets are implemented, and the interrupt requests a shadow register
set, the Nios II processor copies status to
sstatus
, not to
estatus
.
For details about the
sstatus
register, refer to The sstatus Register section.
(8)
The state where both
EH
and
U
are one is illegal and causes undefined results.
(9)
When this field is unimplemented, the field value always reads as 0, and the processor behaves
accordingly.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
50