Related Information
Cache and Tightly-Coupled Memory
8.5.57. ldhu / ldhuio
Instruction
load unsigned halfword from memory or I/O peripheral
Operation
rB ← 0x0000 : Mem16[rA + σ(IMM16)]
Assembler Syntax
ldhu rB, byte_offset(rA)
ldhuio rB, byte_offset(rA)
Example
ldhu r6, 100(r5)
Description
Computes the effective byte address specified by the sum of
rA and the instruction's signed 16-bit immediate value.
Loads register rB with the memory halfword located at the
effective byte address, zero extending the 16-bit value to 32
bits. The effective byte address must be halfword aligned. If
the byte address is not a multiple of 2, the operation is
undefined.
Usage
In processors with a data cache, this instruction may
retrieve the desired data from the cache instead of from
memory. Use the
ldhuio
instruction for peripheral I/O. In
processors with a data cache,
ldhuio
bypasses the cache
and is guaranteed to generate an Avalon-MM data transfer.
In processors without a data cache,
ldhuio
acts like
ldhu
.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A
= Register index of operand rA
B
= Register index of operand rB
IMM16
= 16-bit signed immediate value
Table 104.
ldhu
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
B
IMM16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMM16
0x0b
8. Instruction Set Reference
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
209
