Table 13.
Control Register Names and Bits
Register
Name
Register Contents
0
status
Refer to
The status Register
on page 48
1
estatus
Refer to
The estatus Register
on page 50
2
bstatus
Refer to
The bstatus Register
3
ienable
Internal interrupt-enable bits
The ienable Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
4
ipending
Pending internal interrupt bits
The ipending Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
5
cpuid
Unique processor identifier
6
Reserved
Reserved
7
exception
Refer to
The exception Register
8
pteaddr
Refer to
The pteaddr Register
Available only when the MMU is present. Otherwise
reserved.
9
tlbacc
Refer to
The tlbacc Register
Available only when the MMU is present. Otherwise
reserved.
10
tlbmisc
Refer to
The tlbmisc Register
Available only when the MMU is present. Otherwise
reserved.
11
eccinj
Refer to
The eccinj Register
Available only when ECC is present.
12
badaddr
Refer to
The badaddr Register
13
config
Refer to
The config Register
on page 58
Available when the MPU or ECC is present. Otherwise
reserved.
14
mpubase
Refer to
The mpubase Register
Available only when the MPU is present. Otherwise
reserved.
15
mpuacc
Refer to
The mpuacc Register
for MASK variations table.
Available only when the MPU is present. Otherwise
reserved.
16–31
Reserved
Reserved
The following sections describe the nonreserved control registers.
3.4.2.1. The status Register
The value in the
status
register determines the state of the Nios II processor. All
status
bits are set to predefined values at processor reset. Some bits are exclusively
used by and available only to certain features of the processor, such as the MMU, MPU
or external interrupt controller (EIC) interface.
3. Programming Model
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
48
