Related Information
Nios II Core Implementation Details
on page 121
2.6.2.3.3. Peripheral Region
Nios II cores optionally support a new peripheral region mechanism to indicate
cacheability. The peripheral region cacheability mechanism allows a user at Platform
Designer generation time to specify a region of address space that is treated as non-
cacheable. The peripheral region is any integer power of 2 bytes from a minimum of
4096 bytes up to a maximum of 2 GBytes and must be located at a base address
aligned to the size of the peripheral region. The peripheral region is available as long
as an MMU is not present.
2.6.3. Tightly-Coupled Memory
Tightly-coupled memory provides guaranteed low-latency memory access for
performance-critical applications. Compared to cache memory, tightly-coupled
memory provides the following benefits:
•
Performance similar to cache memory
•
Software can guarantee that performance-critical code or data is located in tightly-
coupled memory
•
No real-time caching overhead, such as loading, invalidating, or flushing memory
Physically, a tightly-coupled memory port is a separate master port on the Nios II
processor core, similar to the instruction or data master port. A Nios II core can have
zero, one, or multiple tightly-coupled memories. The Nios II architecture supports
tightly-coupled memory for both instruction and data access. Each tightly-coupled
memory port connects directly to exactly one memory with guaranteed low, fixed
latency. The memory is external to the Nios II core and is located on chip.
2.6.3.1. Accessing Tightly-Coupled Memory
Tightly-coupled memories occupy normal address space, the same as other memory
devices connected via system interconnect fabric. The address ranges for tightly-
coupled memories (if any) are determined at system generation time.
Software accesses tightly-coupled memory using regular load and store instructions.
From the software’s perspective, there is no difference accessing tightly-coupled
memory compared to other memory.
Note:
The tightly-coupled master requires a fixed memory latency of 1 cycle. Hence, the
transaction with a slave in a different clock domain may not be successful since the
transfer would take more than 1 cycle.
2.6.3.2. Effective Use of Tightly-Coupled Memory
A system can use tightly-coupled memory to achieve maximum performance for
accessing a specific section of code or data. For example, interrupt-intensive
applications can place exception handler code into a tightly-coupled memory to
minimize interrupt latency. Similarly, compute-intensive digital signal processing (DSP)
applications can place data buffers into tightly-coupled memory for the fastest
possible data access.
2. Processor Architecture
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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