The memory address width in the Nios II/f core depends on whether the optional MMU
is present. Without an MMU, the Nios II/f core supports the bit-31 cache bypass
method for accessing I/O on the data master port. Therefore addresses are 31 bits
wide, reserving bit 31 for the cache bypass function. With an MMU, cache bypass is a
function of the memory partition and the contents of the translation lookaside buffer
(TLB). Therefore bit-31 cache bypass is disabled, and 32 address bits are available to
address memory.
5.2.3.1. Instruction and Data Master Ports
The instruction master port is a pipelined Avalon Memory-Mapped (Avalon-MM) master
port. The core also includes a data cache with a fixed 32-byte line size, making he
data master port a pipelined Avalon-MM master port.
The instruction and data master ports on the Nios II/f core are optional. A master port
can be excluded, as long as the core includes at least one tightly-coupled memory to
take the place of the missing master port.
Note:
Although the Nios II processor can operate entirely out of tightly-coupled memory
without the need for Avalon-MM instruction or data masters, software debug is not
possible when either the Avalon-MM instruction or data master is omitted.
Support for pipelined Avalon-MM transfers minimizes the impact of synchronous
memory with pipeline latency. The pipelined instruction and data master ports can
issue successive read requests before prior requests complete.
5.2.3.2. Instruction and Data Caches
This section first describes the similar characteristics of the instruction and data cache
memories, and then describes the differences.
Both the instruction and data cache addresses are divided into fields based on whether
or not an MMU is present in your system.
Table 63.
Cache Byte Address Fields
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
tag
line
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
line
offset
Table 64.
Cache Virtual Byte Address Fields
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
line
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
line
offset
5. Nios II Core Implementation Details
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Nios II Processor Reference Guide
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