Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
0
IMM16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMM16
0x13
Related Information
•
Cache and Tightly-Coupled Memory
•
flushda
on page 199
•
initd
on page 201
•
flushd
on page 198
8.5.51. initi
Instruction
initialize instruction cache line
Operation
Initializes the instruction cache line associated with address
rA.
Assembler Syntax
initi rA
Example
initi r6
Description
Ignoring the tag,
initi
identifies the instruction cache line
associated with the byte address in
ra
, and
initi
invalidates that line.
If the Nios II processor core does not have an instruction
cache, the
initi
instruction performs no operation.
Usage
This instruction is used to initialize the processor’s
instruction cache. Immediately after processor reset, use
initi
to invalidate each line of the instruction cache.
For more information on instruction cache, refer to the
Cache and Tightly Coupled Memory chapter of the Nios II
Software Developer’s Handbook.
Exceptions
Supervisor-only instruction
Instruction Type
R
Instruction Fields
A
= Register index of operand rA
Bit Fields
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
A
0
0
0x29
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x29
0
0x3a
Related Information
Cache and Tightly-Coupled Memory
8. Instruction Set Reference
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
204
