GR740-UM-DS, Nov 2017, Version 1.7
90
www.cobham.com/gaisler
GR740
For a non-cachable write access to the cache, the data is stored in a write buffer and the cache control-
ler issue single write accesses to write the data to memory. The state of the cache is unmodified during
this access.
The cache can accept a non sub-word write hit access every clock cycle. When the cache is unable to
accept a new write access the cache inserts wait-states or issue a AMBA SPLIT response depending
on how the cache is configured.
9.3.3
Cache flushing
The cache can be flushed by accessing a cache flush register. There are three flush modes: invalidate
(reset valid bits), write back (write back dirty cache lines to memory, but no invalidation of the cache
content) and flush (write back dirty cache lines to memory and invalidate the cache line). The flush
command can be applied to the entire cache, one way or to only one cache line. The cache line to be
flushed can be addresses in two ways: direct address (specify way and line address) and memory
address (specify which memory address that should be flushed in the cache. The controller will make
a cache lookup for the specified address and on a hit, flush that cache line). When the entire cache is
flushed the Memory Address field should be set to zero. To invalidate a cache line takes 5 clock
cycles. If the cache line needs to be written back to memory one additional clock cycle is needed plus
the memory write latency. When the whole cache is flushed the invalidation of the first cache line
takes 5 clock cycles, after this one line can be invalidated each clock cycle. When a cache line needs
to be written back to memory this memory access will be stored in an access buffer. If the buffer is
full, the invalidation of the next cache line will stall until a slot in the buffer has opened up. If the
cache also should be disabled after the flush is complete, it is recommended to set the cache disable
bit together with the flush command in the Fush set/index register instead of writing ‘0’ to the cache
enable bit in the cache control register.
Note that after a processor (or any other AHB master) has initiated a flush the processor is not blocked
by the flush unless it writes or requests data from the Level-2 cache. The cache blocks all accesses
(responds with AMBA SPLIT or wait-states depending on cache configuration) until the flush is com-
plete.
9.3.4
Disabling Cache
To be able to safely disable the cache when it is being accessed, the cache need to be disabled and
flushed at the same time. This is accomplished by setting the cache disable bit when issue the flush
command.
9.3.5
Diagnostic cache access
The diagnostic interface can be used for RAM block testing and direct access to the cache tag, cache
data content and EDAC check bits. The read-check-bits field in the error status/control register selects
if data content or the EDAC check bits should be read out. On writes, the EDAC check bits can be
selected from the data-check-bit or tag-check-bit register. These register can also be XOR:ed with the
correct check bits on a write. See the error status/control register for how this is done.
9.3.6
Error injection
Error injection can be performed for data and tag lines either by modifying the value or the checkbits.
The checkbits can be modified by defining a mask that will be XOR:ed with the generated checkbits
or by defining the full checkbits to be written via the tag-check-bit register or data-check-bit-registers.
The value can be modified by performing a diagnostic access while keeping the existing checkbits.
EDAC checkbits can be modified on a regular cache access by setting the xor-check-bit field in the
error status/control register the data EDAC check bits will be XOR:ed with the data-check-bit register
on the next write, or the tag EDAC check bits will be XOR:ed with the tag-check-bit register on the
next tag replacement. The tag check bit manipulation is only done if the tag-check-bit register is not
zero. The xor-check-bit is reset on the next tag replacement or data write. Errors can also be injected
