GR740-UM-DS, Nov 2017, Version 1.7
141
www.cobham.com/gaisler
GR740
12.9.16 ASMP access control registers
Table 145.
0x100 - 0x10C - ASMPCTRL - ASMP access control registers 0 - 3
31
19 18 17 16 15
0
RESERVED
FC SC MC
GRPACCSZCTRL
0
0
0
0
0
r
rw rw rw
rw
31: 19
RESERVED
18
Flush register access control (FC) - If this bit is set to ‘1’ in the ASMP control register at offset
0x100 + n*0x4 then the TLB/cache flush register in ASMP register block n is writable. Otherwise
writes to the TLB/cache flush register in ASMP register block n will be inhibited.
17
Status register access control (SC) - If this bit is set to ‘1’ in the ASMP control register at offset
0x100 + n*0x4 then the Status register in ASMP register block n is writable. Otherwise writes to the
Status register in ASMP register block n will be inhibited.
16
Mask register access control (MC) - If this bit is set to ‘1’ in the ASMP control register at offset
0x100 + n*0x4 then the Master register in ASMP register block n is writable. Otherwise writes to the
Mask register in ASMP register block n will be inhibited.
15:0
Group control register access control (GRPACCSZCTRL) - ASMP register block n’s group access
control field is located at register address offset 0x100 + n*0x4. This field specifies which of the
Group control registers that are writable from an ASMP register block. If GRPACCSZCTRL[i] in
the ASMP access control register at offset 0x100 + n*0x4 is set to ‘1’ then Group control register i is
writable from ASMP register block n.
