GR740-UM-DS, Nov 2017, Version 1.7
135
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GR740
12.9.4 Control register
Table 133.
0x10 - CTRL - Control register
31
21 20
18 17 16 15
12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
PGSZ
LB SP
ITR
DP SIV HPROT AU WP DM GS CE
PM
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
r
rw
rw rw
rw
rw rw
rw
rw rw rw rw rw
rw
rw
31:21
RESERVED
20:18
Page Size (PGSZ) - The value in this field determines the page size mapped by page table entries and
bit vector positions. Valid values are: 000: 4 KiB, 001: 8 KiB, 010: 16 KiB, 011: 32 KiB, 100: 64
KiB, 101: 128 KiB, 110: 256 KiB, 111: 512 KiB
17
Lookup bus (LB) - The value of this bit controls AHB master interface to use for fetching bit vector
and/or page table entries from memory when the core has been implemented with support for multi-
ple buses (multiple AHB master interfaces). If this field is ‘0’, the first master interface will be used
for vector/table lookups. If this field is ‘1’, the second master interface will be used for lookups.
16
SPLIT support (SP) - This implementation of the bridge does not support use of AMBA SPLIT
responses. This bit is read-only with a value of ‘0’.
15:12
IOMMU Translation Range (ITR) - This field defines the size of the address range translated by the
core’s IOMMU functionality. The size of the decoded address range is 16 MiB * 2
ITR
and the
decoded memory area is located on an address with the most significant bits specified by the
TMASK field in Capability register 2, unless ITR = 8 in which case the whole address space is cov-
ered by the translated range.
11
Disable Prefetch (DP) - When this bit is ‘1’ the core will not perform any prefetch operations.
During normal operation prefetch of data improves performance and should be enabled (the value of
this bit should be ‘0’). Prefetching may need to be disabled in scenarios where IOMMU protection is
enabled, which leads to a prefetch operation on every incoming burst access.
10
Save Invalid IOPTE (SIV) - If this field is ‘1’ the core will save IOPTEs that have their valid (V) bit
set to ‘0’ if the core has been implemented with a TLB. If this field is ‘0’ the core will not buffer an
IOPTE with valid (V) set to ‘0’ and perform an page table lookup every time the page covered by the
IOPTE is accessed. If the value of this field is changed, a TLB flush must be made to remove any
existing IOPTEs from the core’s internal buffer. Also if this field is set to ‘0’, any diagnostic accesses
to the TLB should not set the IOPTE valid bit to ‘0’ unless the Tag valid bit is also set to ‘0’.
9:8
HPROT encoding (HPROT) - The value of this field will be assigned to the AMBA AHB HPROT
signal bits 3:2 when the core is fetching protection data from main memory. HPROT(3) signals if the
access is cacheable and HPROT(2) signals if the access is bufferable.
7
Always Update (AU) - If this bit is set to ‘0’ the AHB failing access register will only be updated if
the Access Denied (AD) bit in the Status register is ‘0’ when the access is denied. Otherwise the
AHB failing access register will be updated each time an access is denied, regardless of the Access
Denied (AD) bit’s value.
6
Write Protection only (WP) - If this bit is set to ‘1’ the core will only used the Access Protection Vec-
tor to protect against write accesses. Read accesses will be propagated over the core without any
access restriction checks. This will improve the latency for read operations.
This field has no effect when the core is using IOMMU protection (PM field = “01”).
5
Diagnostic Mode (DM) - If this bit is set to ‘1’ the core’s internal buffers can be accessed via the
Diagnostic interface (see Diagnostic cache access register) when the DE field of the Status register
has been set by the core. Set this bit to ‘0’ to leave Diagnostic mode. While in this mode the core will
not forward any incoming AMBA accesses.
4
Group-Set-addressing (GS) - When this bit is set to ‘1’, the core will use the group number as part of
the Access Protection Vector cache set address.
3
Cache/TLB Enable (CE) - When this bit is set to ‘1’, the core’s internal cache/TLB is enabled.
2:1
Protection Mode (PM) - This value selects the protection mode to use. “00” selects Group Mode and/
or Access Protection Vector mode. “01” selects IOMMU mode.
0
Enable (EN) - Core enable. If this bit is set to 1 the core is enabled. If this bit is set to 0 the core is
disabled and in pass-through mode. After writing this bit software should read back the value. The
change has not taken effect before the value of this bit has changed. The bit transition may be
blocked if the core is in diagnostic access mode or otherwise occupied.
