GR740-UM-DS, Nov 2017, Version 1.7
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16.4.4 Secondary transfer list
The core can be set up with a secondary “asynchronous” transfer list with the same format as the ordi-
nary schedule. This transfer list can be commanded to start at any time during the ordinary schedule.
While the core is waiting for a scheduled command’s slot time to finish, it will check if the next asyn-
chronous transfer’s slot time is lower than the remaining sleep time. In that case, the asynchronous
command will be scheduled.
If the asynchronous command doesn’t finish in time, time will be borrowed from the next command
in the ordinary schedule. In order to not disturb the ordinary schedule, the slot time for the asynchro-
nous messages must therefore be set to pessimistic values.
The exclusive bit in the transfer descriptor can be set if one does not want an asynchronous command
scheduled during the sleep time following the transfer.
Asynchronous messages will not be scheduled while the schedule is waiting for a sync pulse or the
schedule is suspended and the current slot time has expired, since it is then not known when the next
scheduled command will start.
16.4.5 Interrupt generation
Each command in the transfer schedule can be set to generate an interrupt after certain transfers have
completed, with or without error. Invalid command descriptors always generate interrupts and stop
the schedule. Before a transfer-triggered interrupt is generated, the address to the corresponding
descriptor is written into the BC transfer-triggered IRQ ring buffer and the BC Transfer-triggered IRQ
Ring Position Register is incremented.
A separate error interrupt signals DMA errors. If a DMA error occurs when reading/writing descrip-
tors, the executing schedule will be suspended. DMA errors in data buffers will cause the correspond-
ing transfer to fail with an error code (see table 292). See also the AMBA ERROR propagation
description in section 5.10.
Whether any of these interrupt events actually cause an interrupt request on the AMBA bus is con-
trolled by the IRQ Mask Register setting.
16.4.6 Transfer list format
The BC:s transfer list is an array of transfer descriptors mixed with branches as shown in table 289.
Each entry has to be aligned to start on a 128-bit (16-byte) boundary. The two unused words in the
branch case are free to be used by software to store arbitrary data.
Table 289.
GR1553B transfer descriptor format
Offset
Value for transfer descriptor
DMA R/W Value for branch
DMA R/W
0x00
Transfer descriptor word 0 (see table 290)
R
Condition word (see table 294) R
0x04
Transfer descriptor word 1 (see table 291)
R
Jump address, 128-bit aligned
R
0x08
Data buffer pointer, 16-bit aligned.
For write buffers, if bit 0 is set the received
data is discarded and the pointer is ignored.
This can be used for RT-to-RT transfers where
the BC is not interested in the data transferred.
R
Unused
-
0x0C
Result word, written by core (see table 292)
W
Unused
-
