GR740-UM-DS, Nov 2017, Version 1.7
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GR740
Read and write combining is disabled for accesses to the area 0xF0000000 - 0xFFFFFFFF to prevent
accesses wider than 32 bits to register areas.
12.2.6 Core latency
This section deals with latencies in the core’s bridge function. Access protection mechanisms may add
additional delays, please refer to the description of access protection for a description of additional
delays when access protection and/or address translation is enabled.
Table 116 further down shows core behaviour for a single read access.
While the transitions shown in table 116 are simplified they give an accurate view of the core delay. If
the master interface needs to wait for a bus grant or if the read operation receives wait states, these
cycles must be added to the cycle count in the tables.
Table 117 below lists the delays incurred for single operations that traverse the bridge while the bridge
is in its idle state. The second column shows the number of cycles it takes the master side to perform
the requested access, this column assumes that the master slave gets access to the bus immediately
and that each access is completed with zero wait states. The table only includes the delay incurred by
traversing the core. For instance, when the access initiating master reads the core’s prefetch buffer,
each additional read will consume one clock cycle. However, this delay would also have been present
if the master accessed any other slave.
Write accesses are accepted with zero wait states if the bridge is idle, this means that performing a
write to the idle core does not incur any extra latency. However, the core must complete the write
operation on the master side before it can handle a new access on the slave side. If the core has not
BYTE or HALF-WORD single
write
Single access of same size
BYTE or HALF-WORD write burst Incremental write burst of same size and length, the maximum length is the number
of 32-bit words in the write FIFO.
Single read access to any area
Single access of same size
Read burst to prefetchable area
Burst of 128-bit accesses up to 32-byte address boundary.
Read burst to non-prefetchable area
Incremental read burst of same access size as on slave interface, the length is the
same as the length of the incoming burst. The master interface will insert BUSY
cycles between the sequential accesses.
Single write
Single write access of same size
Write burst
Burst write of maximum possible size. The core will use the maximum size (up to
128-bit) that it can use to empty the write buffer.
Table 116.
Example of single read
Clock cycle
Core slave side activity
Core master side activity
0
Discovers access and transitions from idle state
Idle
1
Slave side waits for master side, wait states are
inserted on the AMBA bus.
Discovers slave side transition. Master interface output
signals are assigned.
2
Bus access is granted, perform address phase.
3
Register read data and transition to data ready state.
4
Discovers that read data is ready, assign
HREADY output register and data output regis-
ter.
Idle
5
HREADY is driven on AMBA bus. Core has
returned to idle state
Table 115.
Read and write combining
Access on slave interface
Resulting access(es) on master interface
