COBHAM GR740, User Manual

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GR740-UM-DS, Nov 2017, Version 1.7 423 www.cobham.com/gaisler
GR740
The receiver DMA works in the same way except that it checks if the FIFO is half-full and then per-
forms a burst write to the bus which is half the fifo size in length. The last burst might be shorter. Byte
accesses are used for non word-aligned buffers and/or packet lengths that are not a multiple of four
bytes. There might be 1 to 3 single byte writes when writing the beginning and end of the received
packets.
35.8.1 APB slave interface
As mentioned above, the APB interface provides access to the user registers which are 32-bits in
width. The accesses to this interface are required to be aligned word accesses. The result is undefined
if this restriction is violated.
35.8.2 AHB master interface
The core contains a single master interface which is used by both the transmitter and receiver DMA
engines. The arbitration algorithm between the channels is done so that if the current owner requests
the interface again it will always acquire it. This will not lead to starvation problems since the DMA
engines always deassert their requests between accesses.
The AHB accesses can be of size byte, halfword and word (HSIZE = 0x000, 0x001, 0x010). Byte and
halfword accesses are always NONSEQ.
The burst length will be half the AHB FIFO size except for the last transfer for a packet which might
be smaller. Shorter accesses are also done during descriptor reads and status writes.
The AHB master also supports non-incrementing accesses where the address will be constant for sev-
eral consecutive accesses. HTRANS will always be NONSEQ in this case while for incrementing
accesses it is set to SEQ after the first access. This feature is included to support non-incrementing
reads and writes for RMAP.
BUSY transfer types are never requested and the core provides full support for ERROR (see also the
AMBA ERROR propagation description in section 5.10.), RETRY and SPLIT responses.
35.9 Registers
The core is programmed through registers mapped into APB address space.
Table 552. GRSPW registers
APB address offset Register acronym Register name
0x00 SPW2.CTRL Control
0x04 SPW2.STS Status
0x08 SPW2.DEFADDR Node address
0x0C SPW2.CLKDIV Clock divisor
0x10 SPW2.DKEY Destination key
0x14 SPW2.TC Time
0x18 - 0x1C - RESERVED
0x20 SPW2.DMACTRL DMA control/status, channel 1
0x24 SPW2.DMAMAXLEN DMA RX maximum length, channel 1
0x28 SPW2.DMATXDESC DMA transmit descriptor table address, channel 1
0x2C SPW2.DMARXDESC DMA receive descriptor table address, channel 1
0x30 SPW2.DMAADDR DMA address, channel 1