GR740-UM-DS, Nov 2017, Version 1.7
236
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GR740
15.10.3
Table 274.
0x08 - BCIM - PCI master prefetch burst limit
PCI master prefetch burst limit register
15.10.4
Table 275.
0x0C - AHB2PCI - AHB to PCI mapping for PCI IO
AHB to PCI mapping for PCI IO register
15.10.5
Table 276.
0x10 - DMACTRL - DMA control and status register
DMA control and status register
31
16 15
8
7
0
AHB master unmask
RESERVED
Burst length
0
0
0xFF
rw
r
r
31: 16
AHB master unmask - When bit[n] is set, the prefetch burst of AHB master n is limited by the “Burst
length” field.
15: 8
RESERVED
7: 0
Burst length - Maximum number of beats - 1 in the burst. (Maximin value is 0xFF => 0x100 beats
=> 1kB address)
31
16 15
0
AHB to PCI IO
RESERVED
0
0
rw
r
31: 16
AHB to PCI IO - Used as the MSBs of the base address for a PCI IO access.
15: 0
RESERVED
31 31
20 19
12 11 10
9
8
7
6
4
3
2
1
0
SA
FE
RESERVED
CHIRQ
MA TA PE AE DE
NUMCH
AC
TIV
E
DIS IE EN
1
0
0
0
0
0
0
0
0
0
0
0
0
rw
r
wc
wc wc wc wc wc
rw
r
rw rw rw
31 :
Safety guard (SAFE) - Needs to be set to ‘1’ for the control fields to be updated
30: 20
RESERVED
19: 12
Channel IRQ status (CHIRQ) - Set to ‘1’ when a descriptor is configured to signal interrupt. bit[0]
corresponds to the channel with ID 0, bit[1] corresponds to the channel with ID 1, ... Clear by writing
‘1’
11
Master abort (MA) - received master abort during PCI access. Clear by writing ‘1’
10 :
Target abort (TA) - received target abort during PCI access. Clear by writing ‘1’
9
Parity error (PE) - parity error during PCI access. Clear by writing ‘1’
8 :
AHB data error (AE) - Error during AHB data access. Clear by writing ‘1’
7 :
AHB descriptor error (DE) - Error during descriptor access. Clear by writing ‘1’
6: 4
Number of DMA channels (NUMCH) - Guarded by bit 31, safety guard
3
DMA active (ACTIVE)
2 :
DMA disable/stop (DIS) - Writing ‘1’ to this bit disables the DMA.
1
Interrupt enable (IE) - (Guarded by bit[31], safety guard).
0 :
DMA enable/start (EN) - Writing ‘1’ to this bit enables the DMA
