GR740-UM-DS, Nov 2017, Version 1.7
62
www.cobham.com/gaisler
GR740
6.7.3
AMBA access size
Cacheable data is fetched in a burst 128-bit accesses Data access to uncacheable areas may only be
done with 8-, 16- and 32-bit accesses, i.e. the LDD and STD instructions may not be used. If an area is
marked as cacheable then the data cache will automatically try to use 128-bit accesses. This means
that if 128-bit accesses are unwanted and a memory area is mapped as cacheable then software should
only perform data accesses with cache bypass (ASI 0x1C) and no 64-bit loads (LDD) when accessing
the slave. One example of how to use forced cache miss for loads is given by the following function:
static inline int load(int addr)
{
int tmp;
asm volatile(" lda [%1]0x1c, %0 "
: "=r"(tmp)
: "r"(addr)
);
return tmp;
}
In the GR740 device, this may primarily be of interest when accessing the PROM area (base address
at 0xC0000000) and possibly also for using the processor to test word and sub-word accesses to the
Level-2 cache and memory controller (memory area 0x00000000 - 0x7FFFFFFF).
The processor only supports using wide accesses to memory areas that are marked as cached. This
means that LDD shall not be used for peripheral register areas.
Store instructions result in a AMBA access with size corresponding to the executed instruction, 64-bit
store instructions (STD) are always translated to 64-bit accesses (never converted into two 32-bit
stores as is done for LEON3). The table below indicates the access types used for instruction and data
accesses depending on cachability and cache configuration.
Processor
operation
Area not cacheable
1
Area is cacheable
1
Cache enabled
2
Cache disabled
Instruction
fetch
Burst of 32-bit read accesses
Burst of 128-bit accesses
Data load <=
32-bit
Read access with size specified by load
instruction
Burst of 128-bit accesses
Single accesses can be per-
formed via ASI 0x1C.
Read access with size speci-
fied by load instruction
Data load 64-
bit (LDD)
Illegal
3
Single 64-bit access will be performed
Burst of 128-bit accesses
Single 64-bit read access
Data store <=
32-bit
Store access with size specified by store instruction.
Data store 64-
bit (STD)
Illegal (64-bit store to 32-bit area)
64-bit store access will be performed.
64-bit store access
1
Cached memory regions are 0x00000000 - 0x7FFFFFFF and 0xC0000000 - 0xCFFFFFFF.
2
Bus accesses for reads will only be made on L1 cache miss or on load with forced cache miss.
3
Data accesses to uncached areas may only be done with 8-, 16- and 32-bit accesses.
