GR740-UM-DS, Nov 2017, Version 1.7
131
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GR740
12.7
Statistics
See section 26 for more information.
12.8
ASMP support
In some systems there may be a need to have separated instances of software each controlling a group
of masters. In this case, sharing of the IOMMU register interface may not be wanted as it would allow
software to modify the protection settings for a group of masters that belongs to another software
instance. To prevent this, the core’s register interface is mirrored on different 4 KiB pages. Different
write protection settings can be set for each mirrored block of registers. This allows use of a memory
management unit to control that software running can write to one, and only one, subset of registers.
Four ASMP register blocks are available. Each ASMP register block mirrors the standard register set
described in section 12.9 with the addition that some registers may be write protected. Table 129 con-
tains a column that shows if a register is writable when accessed from an ASMP register block. The
core’s Control register, Master configuration register(s), Diagnostic cache registers, the ASMP access
control register(s) can never be written via ASMP register block. These registers are only available in
the first register set starting at the core register set base address. ASMP register block
n
is mapped at
an offset
n
*0x1000 from the core’s register base address.
Software should first set up the IOMMU and assign the masters into groups. Then the ASMP control
registers should be configured to constrain which registers that can be written from each ASMP block.
After this initialization is done, other parts of the software environment can be brought up.
As an example, consider the case where OS A will control masters 0, 1 and 4 while OS B will control
masters 2 and 3. In this case it may be appropriate to map masters 0, 1 and 4 to group 0 and master 2
and 3 to group 1. The ASMP access control registers can then be configured to only allow accesses to
the Group control register for group 0 from ASMP register block 1 and likewise only allow accesses
to the Group control register for group 1 from ASMP register block 2.
OS A will then map in ASMP register block 1 (registers within page located at core base
0x1000) and OS B will then map in ASMP register block 2 (registers within page located at core base
0x2000). This way OS a will be able to change the base address and the properties of group 0,
containing its masters, without being able to change the protection mechanisms of group 1 belonging
to OS B. Note that since an OS is able to flush the TLB/cache it is able to impact the I/O performance
of masters assigned to other OS instances. Also note that care must be taken when clearing status bits
and setting the mask register that controls interrupt generation.
Table 128.
IOMMU Statistics
Output
Description
hit
High for one cycle during TLB/cache hit.
miss
High for one cycle during TLB/cache miss
pass
High for one cycle during passthrough access
accok
High for one cycle during access allowed
accerr
High for one cycle during access denied
walk
High while core is busy performing a table walk or accessing the access protection vector
lookup
High while core is performing cache lookup/table walk
perr
High for one cycle when core detects a parity error in the APV cache
