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address. The core may be implemented with an Translation Lookaside Buffer (TLB) that may hold a
cached copy of the translation information. Otherwise the translation information will be fetched from
main memory. The base address of the page table to use is given by the Group Configuration register
to which the master performing the access is assigned. Please see the register description of the Group
Configuration register for constraints on the page table base address. The core will use bits X:Y to
index the table, where X depends on the value of the ITR field in the core’s Control register, and Y
depends on the page size (Y = 12 + PGSZ field in Control register).
When the core has fetched the translation information (IOPTE) for the accesses page it will check the
IOPTE’s Valid (V) and Writeable (W) fields. If the IOPTE is invalid, the access will be inhibited. If
the Writeable (W) field is unset and the access is a write access, the access will be inhibited. Other-
wise the core will, for a page size of 4 KiB, use the IOPTE field PPAGE, bits 27:8, and bits 11:0 of the
incoming IO address to form the physical address to use when the access is propagated by the core
(physical address: PPAGE[27:8] & IOADDR[11:0]).
If the valid (V) bit of the IOPTE is ‘0’ the core may or may not store the IOPTE in the TLB. This is
controlled via the SIV field in the core’s Control register.
12.5.2 Prefetch operations and IOMMU protection
During normal bridge operation, and with Access Protection Vector protection, the core determines if
data for an access can be prefetched by looking at the IO address and the System bus plug and play
information. This operation cannot be done without introducing additional delays when the core is
using IOMMU protection. The incoming IO address must first be translated before it can be deter-
mined if the access is to a memory area that can be prefetched. In order to minimize delays the core
makes the assumption that any incoming burst access is to a prefetchable area. The result is that when
using IOMMU protection all burst accesses will result in the core performing a prefetch operation.
12.5.3 Translation Lookaside Buffer operation
The TLB is implemented as a direct-mapped cache with 32 entries, where each entry is 16 bytes, built
up of one data RAM and one tag RAM. The number of locations in each RAM is the number of
entries in the TLB. The width of the data RAM (entry size) is the same as the size of the AMBA
accesses used to fetch page table entries from main memory.
The address used to select a position in the RAMs, called the set address, has
log2(number of entries
in the TLB)
= 5 bits. The number of address bits taken from the physical address required to uniquely
address one position in the TLB depends on the page size. The number of required bits for each
allowed page size is shown in table 120 below, the values in the third to tenth column is the number of
address bits that must be used to accommodate the largest translatable range (maximum value of ITR
field in the core’s Control register). Note that an entry size larger than 32 bits results in an TLB that
holds multiple IOPTEs per entry.
Table 125.
TLB entry size, page size
Entry
size in
bits
Entry
size in
IOPTEs
Bits of physical address needed to identify one position depending on page size
4 KiB
8 KiB
16 KiB
32 KiB
64 KiB
128 KiB
256 KiB
512 KiB
128
4
18
17
16
15
14
13
12
11
