GR740-UM-DS, Nov 2017, Version 1.7
218
www.cobham.com/gaisler
GR740
15
32-bit PCI/AHB bridge
15.1
Overview
The GRPCI2 core is a bridge between the PCI bus and the AMBA AHB bus. The core is capable of
connecting to the PCI bus via both a target and a initiator/master interface. The connection to the
AMBA bus is a AHB master interface for the PCI target functionality and a AHB slave interface for
the PCI initiator functionality. The core also contains a DMA controller. For the DMA functionality,
the core uses the PCI initiator to connect to the PCI bus and an AHB master to connect to the AMBA
bus. Configuration registers in the core are accessible via an AMBA APB slave interface.
The PCI and AMBA interfaces belong to two different clock domains. Synchronization is performed
inside the core through FIFOs.
The PCI interface is compliant with the 2.3 PCI Local Bus Specification.
15.2
Configuration
The core has configuration registers located both in PCI Configuration Space (Compliant with the 2.3
PCI Local Bus Specification) and via an AMBA APB slave interface (for core function control and
DMA control). This section defines which configuration options that are implemented in the PCI con-
figuration space together with a list of capabilities implemented in the core.
15.2.1 Configuration & Capabilities
The implemented configuration can be determined by reading the Status & Capability register acces-
sible via the APB slave interface. The implementation described by this datasheet has the following
characteristics:
•
The PCI vendor 0x1AC8 and device ID 0x0740
•
The PCI class code 0x0B4000 and revision ID 0x00
•
32-bit PCI initiator interface.
•
32-bit PCI target interface
•
DMA controller
Figure 17.
Block diagram
PCI
AHB BUS
PCI BUS
32-bit
32, 64 or 128-bit
PCI
AHB
Master
AHB
Slave
AHB
Master
FIFO
FIFO
FIFO
Target
Initiator
DMA
Ctrl
APB BUS
32-bit
APB
Slave
