GR740-UM-DS, Nov 2017, Version 1.7
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GR740
accept the same address range and the enabled channel with the lowest number will receive the
packet.
Finally, the descriptor table and control register must be initialized. This will be described in the two
following sections.
35.5.4 Setting up the descriptor table address
The core reads descriptors from an area in memory pointed to by the receiver descriptor table address
register. The register consists of a base address and a descriptor selector. The base address points to
the beginning of the area and must start on a 1024 bytes aligned address. It is also limited to be 1024
bytes in size which means the maximum number of descriptors is 128 since the descriptor size is 8
bytes.
The descriptor selector points to individual descriptors and is increased by 1 when a descriptor has
been used. When the selector reaches the upper limit of the area it wraps to the beginning automati-
cally. It can also be set to wrap at a specific descriptor before the upper limit by setting the wrap bit in
the descriptor. The idea is that the selector should be initialized to 0 (start of the descriptor area) but it
can also be written with another 8 bytes aligned value to start somewhere in the middle of the area. It
will still wrap to the beginning of the area.
If one wants to use a new descriptor table, the receiver enable bit in the corresponding DMA channel
control/status register has to be cleared first. When the RX active bit in the same register is cleared it
is safe to update the descriptor table register. When this is finished and descriptors are enabled the
receiver enable bit can be set again.
35.5.5 Enabling descriptors
As mentioned earlier one or more descriptors must be enabled before reception can take place. Each
descriptor is 8 byte in size and the layout can be found in the tables below. The descriptors should be
written to the memory area pointed to by the receiver descriptor table address register. When new
descriptors are added they must always be placed after the previous one written to the area. Otherwise
they will not be noticed.
A descriptor is enabled by setting the address pointer to point at a location where data can be stored
and then setting the enable bit. The WR bit can be set to cause the selector to be set to zero when
reception has finished to this descriptor. IE should be set if an interrupt is wanted when the reception
has finished. The DMA control register interrupt enable bit must also be set for an interrupt to be gen-
erated.
Table 544.
GRSPW receive descriptor word 0 (address offset 0x0)
31 30 29 28 27 26 25 24
0
TR DC HC EP IE WR EN
PACKETLENGTH
31
Truncated (TR) - Packet was truncated due to maximum length violation.
30
Data CRC (DC) - 1 if a CRC error was detected for the data and 0 otherwise.
29
Header CRC (HC) - 1 if a CRC error was detected for the header and 0 otherwise.
28
EEP termination (EP) - This packet ended with an Error End of Packet character.
27
Interrupt enable (IE) - If set, an interrupt will be generated when a packet has been received if the
receive interrupt enable bit in the DMA channel control register is set.
26
Wrap (WR) - If set, the next descriptor used by the GRSPW will be the first one in the descriptor
table (at the base address). Otherwise the descriptor pointer will be increased with 0x8 to use the
descriptor at the next higher memory location. The descriptor table is limited to 1 KiB in size and the
pointer will be automatically wrap back to the base address when it reaches the 1 KiB boundary.
25
Enable (EN) - Set to one to activate this descriptor. This means that the descriptor contains valid con-
trol values and the memory area pointed to by the packet address field can be used to store a packet.
24: 0
Packet length (PACKETLENGTH) - The number of bytes received to this buffer. Only valid after
EN has been set to 0 by the GRSPW.
