GR740-UM-DS, Nov 2017, Version 1.7
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GR740
Field Definitions:
•
Address Tag (ATAG) - Contains the tag address of the cache line.
•
Valid (V) - When set, the cache line contains valid data. The LEON4 caches only have one valid
bit per cache line which is replicated for the whole 8-bit diagnostic field to keep software back-
ward compatibility.
•
CTXID - Context ID, used when MMU is enabled
•
TPAR - Byte-wise parity of tag bits, context ID parity is XOR:ed into bit 3.
•
DPAR - Byte-wise parity of data bits
6.9.6
ASI 0x10, 0x11, 0x13, 0x18 - Flush
For historical reasons there are multiple ASIs that flush the cache in different ways.
Writing to ASI 0x10 will flush the entire instruction cache. If MMU is implemented in the core, both
instruction and data cache will be flushed.
Writing to ASI 0x11 will flush the data cache only.
Writing to ASI 0x13 will flush the instruction cache and data cache. Only available when MMU is
implemented.
Writing to ASI 0x18, which is available only if MMU is implemented, will flush both the MMU TLB,
the I-cache, and the D-cache. This will block execution for a few cycles while the TLB is flushed and
then continue asynchronously with the cache flushes continuing in the background.
Figure 5.
ASI 0xC-0xF address mapping and data layout
0
4
5
11
12
31
(don’t care)
Example for 4 KiB way, 32 bytes/line, 4 ways
Offset
Index
14
Way
15
0
4
5
11
12
31
(don’t care)
(don’t care)
Index
14
Way
15
Data diagnostic ASIs (ASI 0xD,F):
Tag diagnostic ASIs (ASI 0xC,E):
Addr:
0
7
8
9
10
31
VALID
ATAG
0
0
Data:
0
31
Addr:
Data:
Cached data word
0
3
15
31
TPAR
CTXID
Parity:
16
23
Reserved
Reserved
4
0
3
31
DPAR
Parity:
Reserved
4
