GR740-UM-DS, Nov 2017, Version 1.7
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GR740
6.7.4
Error handling
An AHB ERROR response received while fetching instructions will normally case an instruction
access exception (tt=0x1). However if this occurs during streaming on an address that is not needed,
the I cache controller will just not set the corresponding valid bit in the cache tag. If the IU later
fetches an instruction from the failed address, a cache miss will occur, triggering a new access to the
failed address.
An AHB ERROR response while fetching data into the data cache will normally trigger a data_ac-
cess_exception trap (tt=0x9). If the error was for a part of the cache line other than what was currently
being requested by the pipeline, a trap is not generated and the valid bit for that line is not set.
An ERROR response during an MMU table walk will lead the MMU to set the fault type to Internal
error (1) and generate an instruction or data access exception, depending on which type of access that
caused the table walk.
For store operations, see also the AMBA ERROR propagation description in section 5.10.
6.8
Multi-processor system support
This section gives an overview of issues when using the LEON4 in multi-processor configuration.
6.8.1
Start-up
Only the first processor will start after reset, assuming that the BREAK bootstrap signal is low, and all
other processors will remain halted in power-down mode. After the system has been initialized, the
remaining processors can be started by writing to the ‘multiprocessor status register’, located in the
multiprocessor interrupt controller. The halted processors start executing from the reset address (see
section 6.2.18).
An application in a multiprocessor system can determine which processor it is executing on by check-
ing the processor index field in the LEON4 configuration register (%asr17). As all processors typi-
cally have the same reset start address value, boot software must check the processor index and
perform processor specific setup (e.g. initialization of stack pointer) based on the value of the proces-
sor index.
It is only possible for a processor to wake other processors up via the ‘multiprocessor status register’.
Once a processor is running it cannot be reset via the interrupt controller. If software detects that one
processor is unresponsive and needs to restart the processor then the full system should be reset, for
example by triggering the system’s watchdog. In order for software to monitor that all processors in a
system are up and running it is recommended to implement a heartbeat mechanism in software.
6.8.2
Shared memory model
Each processor core has it’s own separate AHB master interface and the AHB controller will arbitrate
between them to share access to the on-chip bus.
If caches are not used, the processors will form a sequentially consistent (SC) system, where every
processor will execute it’s loads, stores and atomics to memory in program order on the AHB bus and
the different processors operations will be interleaved in some order through the AHB arbitration. The
shared memory controller AHB slave is assumed to not reorder accesses so a read always returns the
latest written value to that location on the bus.
When using caches with snooping (and with physical tags if using the MMU), the shared memory will
act according to the slightly weaker SPARC Total Store Order (TSO) model. The TSO model is close
to SC, except that loads may be reordered before stores coming from the same CPU. The stores and
atomics are conceptually placed in a FIFO (see the diagrams in the SPARC standard) and the loads are
allowed to bypass the FIFO if they are not to the same address as the stores. Loaded data from other
addresses may therefore be either older or newer, with respect to the global memory order, than the
stores that have been performed by the same CPU.
