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enabling it in the CCR. This is typically done at the end of the interrupt handler before control is
returned to the interrupted task.
6.3.10 Flushing
Both instruction and data cache are flushed either by executing the FLUSH instruction, setting the FI/
FD bits in the cache control register, or by writing to certain ASI address spaces.
Cache flushing takes one clock cycle per cache set, during which the IU will not be halted, but during
which the caches are disabled. When the flush operation is completed, the cache will resume the state
(disabled, enabled or frozen) indicated in the cache control register. Diagnostic access to the cache is
not possible during a flush operation and will cause a data exception (trap=0x09) if attempted.
Note that while the SPARC V8 specifies only that the instructions pointed to by the FLUSH argument
will be flushed, the LEON4 will additionally flush the entire I and D cache (which is permitted by the
standard as the additional flushing only affects performance and not operation). While the LEON4
currently ignores the address argument, it is recommended for future compatibility to only use the
basic flush %g0 form if you want the full flush behavior.
6.3.11 Locking
Cache line locking is not supported by LEON4.
6.3.12 Diagnostic access
The cache tag and data contents can be directly accessed for diagnostics and for locking purposes via
various ASI:s, see section 6.9.5.
6.3.13 Local scratch pad RAM
Local scratch pad RAM is not supported by LEON4.
6.3.14 Fault tolerance support
The cache memories (tags and data) are protected against soft errors using byte-parity codes. On a
detected parity error, the corresponding cache (I or D) will be flushed and the data will be refetched
from external memory. This is done transparently to software execution.
6.4
Memory management unit
6.4.1
Overview
The memory-management unit is compatible with the SPARC V8 reference MMU (SRMMU) archi-
tecture described inthe SPARC V8 manual, appendix H.
The MMU provides address translation of both instructions and data via page tables stored in mem-
ory.When needed, the MMU will automatically access the page tables to calculate the correct physical
address. The latest translations are stored in a special cache called the translation lookaside buffer
(TLB), also referred to as Page Descriptor Cache (PDC) in the SRMMU specification. The MMU also
provides access control, making it possible to “sandbox” unpriviledged code from accessing the rest
of the system.
6.4.2
MMU/Cache operation
When the MMU is disabled, the MMU is bypassed and the caches operate with physical address map-
ping. When the MMU is enabled, the caches tags store the virtual address and also include an 8-bit
context field. Both the tag address and context field must match to generate a cache hit. If cache
snooping is used, physical tags must be enabled for it to work when address translation is used, see
section 6.3.7.
