GR740-UM-DS, Nov 2017, Version 1.7
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executing instruction will take trap 0x2b. This trap can be disabled using the DWT configuration (see
section 6.10.3). See also the AMBA ERROR propagation description in section 5.10.
Note: a 0x2b trap handler should flush the data cache, since a write hit would update the cache while
the memory would keep the old value due the write error
6.3.6
Operating with MMU
When MMU is enabled, the virtual addresses seen by the running code no longer correspond directly
to the physical addresses on the AHB bus. The cache uses tags based on the virtual addresses, as this
avoids having to do any additional work to translate the address in the most timing-critical hit case.
However, any time a bus access needs to be made, a translation request has to be sent to the MMU to
convert the virtual address to a physical address. For the write buffer, this work is included in the
background processing of the store. The translation request to the MMU may result in memory
accesses from the MMU to perform table walk, depending on the state of the MMU.
The MMU context ID is included in the cache tags in order to allow switching between multiple
MMU contexts mapping the same virtual address to different physical addresses. Note that the cache
does not detect aliases to the same physical address so in that case the same physical address may be
cached in multiple ways (also see snooping below).
Note:
The processor requires cachable areas to support wide (128-bit) bus accesses. The MMU must
not be used to mark uncacheable areas (such as AMBA plug&play and PCI memory space) as cache-
able since this will violate the requirements in section 6.7.3.
6.3.7
Snooping
The data cache supports AHB bus snooping. The AHB bus the processor is connected to, is monitored
for writes from other masters to an address which is in the cache. If a write is done to a cached
address, that cache line is marked invalid and the processor will be forced to fetch the (new) data from
memory the next time it is read.
For using snooping together with the MMU, an extra tag memory storing physical tags is used to
allow comparing with the physical address on the AHB bus.
The processor can snoop on itself and invalidate any other cache lines aliased to the same physical
address in case there are multiple virtual mappings to the same physical address that is being written.
However, note that this does not happen until the write occurs on the bus so the other virtual aliases
will return the old data in the meantime.
6.3.8
Enabling and disabling cache
Both I and D caches are disabled after reset. They are enabled by writing to the cache control register
(see 6.10.6). Before enabling the caches after a reset they must be flushed to ensure that all tags are
marked invalid.
6.3.9
Cache freeze
Each cache can be in one of three modes: disabled, enabled and frozen. If disabled, no cache operation
is performed and load and store requests are passed directly to the memory controller. If enabled, the
cache operates as described above. In the frozen state, the cache is accessed and kept in sync with the
main memory as if it was enabled, but no new lines are allocated on read misses.
If the DF or IF bit is set, the corresponding cache will be frozen when an asynchronous interrupt is
taken. This can be beneficial in real-time system to allow a more accurate calculation of worst-case
execution time for a code segment. The execution of the interrupt handler will not evict any cache
lines and when control is returned to the interrupted task, the cache state is identical to what it was
before the interrupt. If a cache has been frozen by an interrupt, it can only be enabled again by
