GR740-UM-DS, Nov 2017, Version 1.7
138
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GR740
12.9.8 AHB failing access register
Table 137.
0x20 - AHBFAS - AHB failing access register
12.9.9 Master configuration registers
Table 138.
0x40 - 0x64 - MSTCFG0-9 - Master configuration register 0 - 9
31
5
4
3
2
1
0
FADDR[31:5]
FW
FMASTER
0
0
0
r
r
r
31:5
Failing Address (FADDR[31:5]) - Bits 31:5 of IO address in access that was inhibited by the core.
This field is updated depending on the value of the Control register AU field and the Status register
AD field.
4
Failing Write (FW) - If this bit is set to ‘1’ the failed access was a write access, otherwise the failed
access was a read access. This field is updated depending on the value of the Control register AU
field and the Status register AD field.
3:0
Failing Master (FMASTER) - Index of the master that initiated the failed access. This field is
updated depending on the value of the Control register AU field and the Status register AD field.
31
24 23
12 11
5
4
3
0
VENDOR
DEVICE
RESERVED
BS
GROUP
*
*
0
0
0
r
r
r
rw
rw
31: 24
Vendor ID (VENDOR) - GRLIB Plug’n’play Vendor ID of master
23: 12
Device ID (DEVICE) - GRLIB Plug’n’play Device ID of master
11: 5
RESERVED
4
Bus select for master (BS) - Master n’s bus select register is located at register address offset 0x40 +
n*0x4. This field specifies the bus to use for accesses initiated by AHB master n. A ‘0’ in this field
routes master accesses to the Processor AHB bus. A ‘1’ in this field routes master accesses to the
Memory AHB bus. Note that the value in this field affects bus selection even if the IOMMU is dis-
abled.
3:0
Group assignment for master - Master n’s group assignment field is located at register address offset
0x40 + n*0x4. This field specifies the group to which a master is assigned.
