GR740-UM-DS, Nov 2017, Version 1.7
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www.cobham.com/gaisler
GR740
5
Technical notes
5.1
GRLIB AMBA plug&play scanning
The bus structure in this design requires some special consideration with regard to plug&play scan-
ning. The default behavior of GRLIB AMBA plug&play scanning routines is to start scanning at
address 0xFFFFF000. If any AHB/AHB bridges, APB bridges or L2 cache controllers are detected
during the scan, the general scanning routine traverses the bridge and reads the plug&play informa-
tion from the bus behind the bridge. In this design, the default 0xFFFFF000 address gives plug&play
information for the Processor AHB bus. This plug&play area contains information which allows soft-
ware to detect all devices on the Processor, Slave I/O, Master I/O and Memory AHB buses.
The plug&play information on the Processor bus does not contain any references to the plug&play
information on the Debug AHB bus, nor can the peripherals on the Debug AHB bus be accessed from
the Processor AHB bus as the buses are connected using a uni-directional bridge. In order to detect the
peripherals on the Debug AHB bus, the debug monitor used must be informed about the memory map
of the bus, or be instructed to start plug&play scanning at address 0xEFFFF000 from where all the
other plug&play areas in the system can be found.
Depending on the debug monitor used, the monitor may detect that it connects to a GR740 design and
start scanning on the Debug AHB bus (this applies to GRMON2 from Cobham Gaisler). Otherwise
the address 0xEFFFF000 should be specified to the monitor. In the case where the monitor detects that
it is connected to a GR740 design, it may be necessary to force the monitor to start scanning at the
default address 0xFFFFF000 when connecting with a debug monitor through the Master I/O bus, from
which the Debug AHB bus cannot be accessed (this is not required for GRMON2).
5.2
Processor register file initialisation and data scrubbing
Please refer to section 6.11.
5.3
PROM-less systems and SpaceWire RMAP
The system has support for PROM less operation where system software is uploaded by an external
entity. In order to allow system software to be uploaded via RMAP the bootstrap signal GPIO[11]
should be low in order to not clock gate off the SpaceWire router after system reset. The IOMMU will
be in pass-through after reset allowing an external entity to upload software, change the processor
reset start address, and wake the processors up via the multiprocessor interrupt controller’s register
interface. In order to prevent the processor from starting execution, the external BREAK signal
should be asserted (and the DSU needs to be disabled, see bootstrap signal descriptions in section
3.1). This will also prevent the timer unit’s watchdog timer from being started. Note that the PLL
watchdog described in section 4.6 will still be active and external units must either pet this watchdog
or have the WDOGN signal disconnected from reset circuitry to prevent reset of the device.
If the system has a boot PROM available it is recommended to have the SpaceWire router gated off
after reset by setting the bootstrap signal GPIO[11] high during system reset. If router functionality
needs to be immediately available, the designer should consider disabling RMAP or enable IOMMU
protection early in the software boot process so that external entities cannot interfere with system
operation. It takes 20 microseconds for the SpaceWire links to enter run state. Before that, incoming
RMAP traffic cannot enter the system. This leaves time (4000 cycles at 200 MHz system frequency)
for the processors to disable RMAP via a register write, or to set up rudimentary IOMMU protection.
Additional information and example software is available in [SPWBT].
