GR740-UM-DS, Nov 2017, Version 1.7
299
www.cobham.com/gaisler
GR740
Table 372.
0x08 - CONFIG- Configuration register
31
14 13 12 11 10
9
8
7
3
2
0
RESERVED
EV ES EL EE DF SI
IRQ
TIMERS
0
0
0
0
0
0
1
*
*
r
rw rw rw rw rw
r
r
r
31: 14
RESERVED
13
External Events (EV). If set then the latch events are taken from the secondary input. If this field is
zero then the source of the latch events is the interrupt bus.
12
Enable set (ES). If set, on the next matching interrupt, the timers will be loaded with the correspond-
ing timer reload values. The bit is then automatically cleared, not to reload the timer values until set
again.
11
Enable latching (EL). If set, on the next matching interrupt, the latches will be loaded with the corre-
sponding timer values. The bit is then automatically cleared, not to load a timer value until set again.
10
Enable external clock source (EE). If set the prescaler is clocked from the external clock source.
9
Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise the debug support unit
can freeze the timer unit when processors enter debug mode.
8
Separate interrupts (SI). Reads ‘1’ if the timer unit generates separate interrupts for each timer, oth-
erwise ‘0’.
7: 3
APB Interrupt: If configured to use common interrupt all timers will drive the same interrupt line,
otherwise timer
n
will drive the first interrupt line assigned to the core+
n
. GPTIMER 0 has one ded-
icated interrupt for each timer, GPTIMER unit 1 to 4 have one shared interrupt line for all timers.
2: 0
Number of implemented timers (TIMERS) - Timer unit 0 has five timers, timer unit 1 - 4 has four
timers.
Table 373.
0x0C - LATCHCFG - Timer latch configuration register
31
14 13 12 11 10
9
8
7
4
3
2
0
RESERVED
LATCHSEL
0
0
r
rw
31: 5
RESERVED
4: 0
Latch select (LATCHSEL) - Specifies what bits of the interrupt bus, or external latch vector, bus that
shall cause the Timer Latch Registers to latch the timer values. If the configuration register EV field
is zero then latching is done based on events on the interrupt bus. If the EV field is ‘1’ then the exter-
nal latch vecor is used and the following events can be used:
Position 0: MIL-STD-1553B controller RTSYNC event. Time will be latched when a valid com-
mand is detected by the controller. Time latching will be disabled when a RTSYNC event is reported
by the MIL-STD-1553B controller.
Position 1: Connectef to SpaceWire router tick out 0
Position 2: Connectef to SpaceWire router tick out 1
Position 3: Connectef to SpaceWire router tick out 2
Position 4: Connectef to SpaceWire router tick out 3
Table 374.
0xn0 where n selects the timer - TCNTVALn - Timer n counter value register
31
0
TCVAL
0
rw
31: 0
Timer Counter value (TCVAL) - Decremented by 1 for each prescaler tick.
