GR740-UM-DS, Nov 2017, Version 1.7
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GR740
13.4.4.6 Setting up the DMA control register
The final step to receive packets is to set the control register as follows: The receiver must first be
enabled by setting the rxen bit in the DMA control register (see section 13.4.8). The rxdescav bit in
the DMA control register is then set to indicate that there are new active descriptors. This must always
be done after the descriptors have been enabled or the port might not notice the new descriptors. More
descriptors can be activated when reception has already started by enabling the descriptors and writ-
ing the rxdescav bit. When these bits are set, reception will start immediately when data is arriving.
13.4.4.7 The effect to the control bits during reception
When the receiver is disabled, all packets going to the DMA-channel are discarded if the address of
the packet does not fall into the range of another DMA channel. If the receiver is enabled and the
address falls into the accepted address range, the next state is entered where the rxdescav bit is
checked. This bit indicates whether there are active descriptors available or not and should be set by
the external application using the DMA channel each time descriptors are enabled as mentioned
above. If the rxdescav bit is ‘0’ and the nospill bit is ‘0’ the packets will be discarded. If nospill is ’1’
the AMBA port waits until rxdescav is set and the characters are kept in the N-Char FIFO during this
time. If the FIFO becomes full, back-pressure is applied to the SpaceWire link by ceasing the trans-
mission of FCTs.
When rxdescav is set, the next descriptor is read and - if enabled - the packet is received to the buffer.
If the read descriptor is not enabled, however, rxdescav is set to ‘0’ and the packet is spilled depend-
ing on the value of nospill.
The receiver can be disabled at any time, which will stop packets from being received to this channel.
If a packet is currently received when the receiver is disabled, the reception will continue until it is
finished. The rxdescav bit can also be cleared at any time. It will not affect any ongoing receptions but
no more descriptors will be read until it is set again. Rxdescav is also cleared by the port when it reads
a disabled descriptor.
13.4.4.8 Status bits
When the reception of a packet is finished, the enable bit in the current descriptor is set to zero. When
enable is zero, the status bits are also valid and the number of received bytes is indicated in the length
field. The DMA control register contains a status bit, which is set each time a packet has been
received. The port can also be set up to generate an interrupt for this event.
The RMAP CRC calculation is always active for all received packets and the full payload of the
packet without the EOP/EEP is covered. The packet is always assumed to be an RMAP packet and the
length of the header is determined by checking byte 3 that should be the command field. The calcu-
lated CRC value is then checked when the header has been received (according to the calculated num-
ber of bytes) and if it is non-zero the HC bit is set indicating a header CRC error.
The CRC value is not reset after the header has been received, instead the calculation continues until
the complete packet has been received. Then, if the CRC value is non-zero, the DC bit is set to indi-
cate a data CRC error. This means that the port can indicate a data CRC error even if the data field was
correct but the header CRC was incorrect. Thus, a CRC data error is only determinate when the HC
bit is zero.
Table 147.
RXDMA receive descriptor word 1 (address offset 0x4)
31
0
PACKETADDRESS
31: 0
Packet address (PACKETADDRESS) - The address pointing at the buffer which will be used to store
the received packet.
