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COBHAM GR740, User Manual

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GR740-UM-DS, Nov 2017, Version 1.7

86

www.cobham.com/gaisler

GR740

9

Level 2 Cache controller

9.1

Overview

The L2 cache works as an AHB to AHB bridge, caching the data that is read or written via the bridge.
The cache is a unified cache and data may exist in both the processor Level-1 caches and the Level-2 
cache, or only in a Level-1 or the Level-2 cache. A front-side AHB interface is connected to the Pro-
cessor AHB bus, while a backend AHB interface is connected to the Memory AHB bus. Figure 8 
shows a system block diagram for the cache controller.
Note that the L2 cache is disabled after reset and should be enabled by boot software.

9.2

Operation

The Level-2 cache is implemented as a multi-way cache with an associativity of four. The replace-
ment policy can be configured as: LRU (least-recently-used), pseudo-random or master-index (where 
the way to replace is determine by the master index). The way size is 512 KiB with a line size of 32 
bytes.

9.2.1

Replacement policy

The cache supports three different replacement policies: LRU (least-recently-used), (pseudo-) random

 

and master-index. The reset value for replacement policy is LRU. 
With the master-index replacement policy, master 0 would replace way 1, master 1 would replace way 
2 and so on. For master indexes corresponding to a way number larger than the number of imple-
mented ways there are two options to determine which way to replace. One option is to map all these 
master index to a specific way. This is done by specifying this way in the index-replace field in the 
control register and selecting this option in the replacement policy field also located in the control reg-
ister. It is not allowed to select a locked way in the index-replace field. The second option is to replace 
way = ((master index) modulus (number of ways)). This option can be selected in the replacement 
policy field. 

9.2.2

Write policy

The cache can be configured to operate as write-through or copy-back cache. Before changing the 
write policy to write-through, the cache has to be disabled and flushed (to write back dirty cache lines 
to memory). This can be done by setting the Cache disable bit when issue a flush all command. The 

Figure 8.  

Block diagram

CPU

Memory

L2C

CPU

Controller

Memory AHB bus

Processor AHB bus

Summary of Contents for GR740

Page 1: ...000 Mbit Ethernet interfaces Specification System frequency 250 MHz Main memory interface PC100 SDRAM SpaceWire router with SpaceWire links 300 Mbit s 33 MHz PCI 2 3 initiator target interface Etherne...

Page 2: ...signal list 32 3 5 Pin driver configuration 35 4 Clocking and reset 36 4 1 Clock inputs 36 4 2 Clock loop for SDRAM 36 4 3 Reset scheme 37 4 4 Clock multiplexing for main system clock SDRAM and Space...

Page 3: ...oating point Unit 82 8 1 Overview 82 8 2 Functional description 82 9 Level 2 Cache controller 86 9 1 Overview 86 9 2 Operation 86 9 3 Operation 89 9 4 Registers 92 10 SDRAM Memory Controller with Reed...

Page 4: ...Target interface 228 15 6 DMA Controller 229 15 7 PCI trace buffer 232 15 8 Interrupts 232 15 9 Reset 233 15 10 Registers 233 16 MIL STD 1553B AS15531 Interface 241 16 1 Overview 241 16 2 Electrical i...

Page 5: ...1 21 2 Operation 301 21 3 Registers 306 22 General Purpose I O Ports 316 22 1 Overview 316 22 2 Operation 316 22 3 Registers 317 23 UART Serial Interfaces 323 23 1 Overview 323 23 2 Operation 323 23 3...

Page 6: ...AHB bus to Processor AHB bus 385 32 1 Overview 385 32 2 Operation 385 32 3 Registers 388 33 LEON4 Hardware Debug Support Unit 389 33 1 Overview 389 33 2 Operation 389 33 3 AHB Trace Buffer 390 33 4 In...

Page 7: ...maximum ratings 438 39 2 Recommended DC operating conditions 438 39 3 Input and output signal DC characteristics 439 39 4 Power supplies 439 39 5 AC characteristics 441 40 Mechanical description 458...

Page 8: ...ct 1 3 Updates and feedback Updates are available at http www gaisler com gr740 Feedback can be sent to Cobham Gaisler AB support support gaisler com For commercial questions please contact sales gais...

Page 9: ...Wire Links nodes routers and networks ECSS E ST 50 12C July 2008 SPWBT Booting a LEON system over SpaceWire RMAP GRLIB AN 0002 http www gaisler com notes SPWCUC High Accuracy Time Synchronization over...

Page 10: ...d in GRPCI2 section 20 1 2 2016 January Correct name of TOV field in DSU Instruction trace buffer control register 1 Add note about pulsed interrupts in interrupt controller section Update footer 1 3...

Page 11: ...ug Link section Clarify signal names in pin multiplexing tables 24 and 25 Add pin driver configuration section 3 5 add reference in section 13 1 Remove references to PC133 SDRAM operation Added placem...

Page 12: ...struction trace buffer sizes in section 2 1 Add note about using the MMU to mark memory as cacheable in section 6 3 6 Describe SDRAM bus parking functionality in section 10 6 2 Update description of S...

Page 13: ...Error Detection and Correction EDCL Ethernet Debug Communication Link FIFO First In First Out refers to buffer type FPU Floating Point Unit Gb Gigabit 109 bits GB Gigabyte 109 bytes GiB Gibibyte gigab...

Page 14: ...umber and the LSb the lowest bit number 1 10 2 Radix The following conventions is used for writing numbers Binary numbers are indicated by the prefix 0b e g 0b1010 Hexadecimal numbers are indicated by...

Page 15: ...2 EF2 Field description 15 8 Example field 1 EF1 Field description 7 0 Example field 0 EF0 Field description Table 4 Reset value definitions Value Description 0 Reset value 0 1 Reset value 1 Used for...

Page 16: ...interface connected to the Memory AHB bus The AHB master interface to use when propagating traffic from a peripheral on the Master I O AHB bus is dynamically configurable Peripheral unit register inte...

Page 17: ...gement Unit IOMMU with support for eight groups of DMA units 8 port SpaceWire router switch with four on chip AMBA ports with RMAP SpaceWire TDP controller 2x 10 100 1000 Mbit Ethernet MAC 32 bit 33 M...

Page 18: ...GPTIMER Modular timer unit with watchdog 20 0x01 0x011 GR1553B MIL STD 1553B AS15531 interface 16 0x01 0x04D GRCAN CAN 2 0 controller with DMA 17 0x01 0x03D GRCLKGATE Clock gating unit 25 0x01 0x02C...

Page 19: ...82000 0xFF8FEFFF Unused Slave I O 0xFF8FF000 0xFF8FFFFF Slave I O bus plug play area Slave I O APBBRIDGE0 0xFF900000 0xFF9FFFFF APB bridge 0 Processor A P B B R I D G E 0 APBUART0 0xFF900000 0xFF9000F...

Page 20: ...000FF PCI controller registers Processor GRCAN0 0xFFA01000 0xFFA013FF CAN 2 0 controller 0 Processor GRCAN1 0xFFA02000 0xFFA023FF CAN 2 0 controller 1 Processor SPICTRL 0xFFA03000 0xFFA030FF SPI contr...

Page 21: ...sor 3 APBBRIDGED 0xE4000400 0xE40FFFFF APB bridge on Debug AHB bus A P B D GRSPW2 0xE4000000 0xE40000FF SpaceWire RMAP target with AMBA interface L4STAT 0xE4000200 0xE40003FF LEON4 Statistics unit sec...

Page 22: ...le for use by software for inter processor and inter process synchronization 13 Unassigned 14 Unassigned 15 Unassigned Note Not maskable by processor 16 GRGPIO0 1 CAN The GPIO port has configuration r...

Page 23: ...rocessor 0xFFFFF020 0xFFFFF03F LEON4 2 LEON4 SPARC V8 Processor 0xFFFFF040 0xFFFFF05F LEON4 3 LEON4 SPARC V8 Processor 0xFFFFF060 0xFFFFF07F GRIOMMU 4 AHB AHB bridge with protection functionality 0xFF...

Page 24: ...040 0xEFFFF05F GRETH_GBIT EDCL 1 3 10 100 1000 Mbit Ethernet Debug Communication Link 0xEFFFF060 0xEFFFF07F Table 15 Plug play information for slaves on Debug AHB bus Slave Index Function Address rang...

Page 25: ...index information for slaves on Master I O AHB bus Slave Index Function Address range GRIOMMU 0 IOMMU slave interface Not applicable Table 20 Plug play information for APB slaves connected via the fi...

Page 26: ...F028 0xFFAFF02F AHBSTAT 6 AHB Status register interface 0xFFAFF030 0xFFAFF037 AHBSTAT 7 AHB Status register interface 0xFFAFF038 0xFFAFF03F GRGPIO 8 General purpose I O port 0xFFAFF040 0xFFAFF047 GRGP...

Page 27: ...g after reset PCIMODE_ENABLE Enables PCI mode If the bootstrap signal MEM_IFWIDTH is HIGH then PCIMODE_EN ABLE selects if the top half of the SDRAM interface should be used for the PCI controller HIGH...

Page 28: ...Note that it is the top part of the data bus PRO MIO_DATA 15 8 that is used for the PROM in 8 bit mode GPIO 7 6 Selects SpaceWire router Distributed Interrupt configuration 00 Interrupts with acknowl...

Page 29: ...it position Pin name Primary function Alternative function GPIO2 function Register bank FTMEN ALTEN bit position Signal Dir Signal Dir Signal Dir PROMIO_ADDR 27 as pin name O UART0_TXD O GPIO2 21 IO 2...

Page 30: ...DTH PCIMODE_ENABLE SDRAM interface Ethernet port 1 PCI 0 0 64 data bits 32 check bits Unavailable Unavailable 1 1 0 32 data bits 16 check bits Available Unavailable 1 Unavailable Available Table 27 Mu...

Page 31: ...O none I PCI_CBE 2 IO MEM_DQ 45 as pin name IO none I PCI_CBE 1 IO MEM_DQ 44 as pin name IO none I PCI_CBE 0 IO MEM_DQ 43 as pin name IO none I PCI_FRAME IO MEM_DQ 42 as pin name IO none I PCI_REQ O M...

Page 32: ...VE Debug Support Unit active signal No Out High PCIMODE_ENABLE Enables PCI mode See description of boot strap signals No In High MEM_CLKSEL Memory interface external clock select sig nal No In MEM_IFW...

Page 33: ...net port 1 Receiver data See 3 3 2 In ETH1_RXDV Ethernet port 1 Receive data valid See 3 3 2 In High ETH1_RXCLK Ethernet port 1 receiver clock See 3 3 2 In ETH1_COL Ethernet port 1 Collision detected...

Page 34: ...PCI Interrupt D See 3 3 2 In Low PCI_REQ PCI Request signal See 3 3 2 Out Low PCI_M66EN PCI 66 MHz enable signal See 3 3 2 In High PROM_CEN 1 0 PROM chip select See 3 3 1 Out Low PROMIO_ADDR 27 0 PRO...

Page 35: ...3 3 1 Out High GR1553_BUSBRXP MIL STD 1553 Bus B receiver positive input See 3 3 1 In High GR1553_BUSBRXN MIL STD 1553 Bus B receiver negative input See 3 3 1 In High GR1553_BUSBTXIN MIL STD 1553 Bus...

Page 36: ...or phase to the clock going out the loop or any other clock in the system Other ways of generating the SDRAM clocks such as external PLL s are also possible Note The external feedback loop is always r...

Page 37: ...SYS_EXTLOCK signal is never ignored Since all the lock signals are available on pack age pins custom lock handling can be implemented on board level The bootstrap signal sampling the general purpose r...

Page 38: ...k Gating Unit Gated CPU FPU and peripheral clocks control registers cpu idle System clock SPWPLL spw_clk to SPW codec gr1553_clk eth0 clk jtag_tck to 1553 codec to GRETH0 to TAP and scan chain 1 0 mem...

Page 39: ...urations are invalid and may lead to malfunction Note also that when overclocking the device by exceeding the maximum clock frequencies given in the datasheet correct functionality is not guaranteed a...

Page 40: ...MHz clock for the MIL STD 1553B codec is taken from the dedicated pin GR1553_CLK 4 9 Clock gating unit The design has a clock gating unit through which individual units can have their AHB clocks enabl...

Page 41: ...Mbit value after the PHY has entered 1000 Mbit operation When this happens the system will not be able to transmit Ethernet traffic When the Ethernet debug communication link EDCL is enabled then the...

Page 42: ...r through the Master I O bus from which the Debug AHB bus cannot be accessed this is not required for GRMON2 5 2 Processor register file initialisation and data scrubbing Please refer to section 6 11...

Page 43: ...policies based on AHB master bus index This means that the L2 cache can be configured so that one processor cannot evict data allocated by accesses from another processor The system does not provide f...

Page 44: ...ible option is using the MMU address translation inside each partition to map the virtual address space to physical address ranges that can never end up in the same level 2 sets only physical addresse...

Page 45: ...Note however that the generic docu mentation may describe functionality not present in this implementation and that this datasheet super sedes any IP core documentation 5 7 3 Plug and play Standard G...

Page 46: ...vailable timers The following timers are available in the system Processor up counter The up counters accessible via internal registers ASR22 and ASR23 in the processors provide a 56 bit value see sec...

Page 47: ...eady completed This means that peripherals capable of DMA and the proces sors may perform write accesses to unmapped areas memory with uncorrectable errors and write pro tected regions without seeing...

Page 48: ...ht The pipeline consists of 7 stages with a separate instruction and data cache interface 6 1 2 Cache sub system LEON4 has a cache system consisting of a separate instruction and data cache Both cache...

Page 49: ...via the debug interface 6 1 6 Interrupt interface LEON4 supports the SPARC V8 interrupt model with a total of 15 asynchronous interrupts The inter rupt interface provides functionality to both generat...

Page 50: ...ht register windows Hardware multiplier and Radix 2 divider non restoring Static branch prediction Single vector trapping for reduced code size Figure 3 LEON4 integer unit datapath diagram alu shift m...

Page 51: ...at can extend an instructions duration in the pipeline are listed in the table and text below Branch interlock When a conditional branch or trap is performed 1 2 cycles after an instruction which modi...

Page 52: ...and UMULCC performs unsigned multiply UMULCC and SMULCC also set the condition codes to reflect the result The multiply instructions are performed using a 32x32 pipelined hardware multiplier 6 2 6 Mu...

Page 53: ...x0B is generated 6 2 11 Instruction trace buffer The instruction trace buffer consists of a circular buffer that stores executed instructions This is enabled and accessed only through the processor s...

Page 54: ...match Precise window_overflow 0x05 8 SAVE into invalid window Precise window_underflow 0x06 8 RESTORE into invalid window Precise mem_address_not_aligned 0x07 10 Memory access to un aligned address P...

Page 55: ...nters this idle mode Note asr19 must always be written with the data value zero to ensure compatiblity with future extensions Note This instruction must be performed in supervisor mode with interrupts...

Page 56: ...oth caches is described in section 6 7 2 6 3 2 Cache operation Each cache controller has two main memory blocks the tag memory and the data memory At each address in the tag memory a number of cache e...

Page 57: ...any following instruction that requires bus access will block until the write buffer has been emptied Loads served from cache will however not block due to the cache policy used there can not be a mi...

Page 58: ...The AHB bus the processor is connected to is monitored for writes from other masters to an address which is in the cache If a write is done to a cached address that cache line is marked invalid and t...

Page 59: ...ctly accessed for diagnostics and for locking purposes via various ASI s see section 6 9 5 6 3 13 Local scratch pad RAM Local scratch pad RAM is not supported by LEON4 6 3 14 Fault tolerance support T...

Page 60: ...and double precision operands and implements all SPARC V8 FPU operations including square root and division The FPU is interfaced to the LEON4 pipeline using a LEON4 specific FPU controller GRFPC that...

Page 61: ...e types of AMBA accesses supported and performed by the processor depend on the accessed memory area s cachability if the corresponding cache is enabled and if the accessed memory area has been marked...

Page 62: ...hat LDD shall not be used for peripheral register areas Store instructions result in a AMBA access with size corresponding to the executed instruction 64 bit store instructions STD are always translat...

Page 63: ...uration register asr17 As all processors typi cally have the same reset start address value boot software must check the processor index and perform processor specific setup e g initialization of stac...

Page 64: ...a sequentially consistent manner Since software drivers usu ally expect to be alone accessing the peripheral and the peripheral s register interfaces are not designed for concurrent use by multiple m...

Page 65: ...systems without cache coherency to load data that may have changed in the back ground for example by DMA units It can also be used for other reasons for example diagnostic pur poses to force a AHB loa...

Page 66: ...nstruction cache memories These ASIs should only be accessed by 32 bit LDA STA instructions These ASIs can not be used while a cache flush is in prog ress The same address bits used normally as index...

Page 67: ...the core both instruction and data cache will be flushed Writing to ASI 0x11 will flush the data cache only Writing to ASI 0x13 will flush the instruction cache and data cache Only available when MMU...

Page 68: ...ul for RAM testing and should not be performed during normal operation This ASI is addressed the same way as the regular diagnostic ASI s 0xC 0xE and the read written data has the layout as shown belo...

Page 69: ...o 0011 3 for LEON3 LEON4 23 20 Integer condition codes ICC see sparcv8 for details 19 14 Reserved 13 Enable coprocessor EC read only 12 Enable floating point EF 11 8 Processor interrupt level PIL cont...

Page 70: ...register file protection register 31 4 3 2 1 0 RESERVED FPCE IUCE 0 0 0 r rw rw 31 4 RESERVED 3 2 FP register file correctable error FPCE Flag set when a correctable error has been detected in the FP...

Page 71: ...Branch Prediction on instruction cache misses DBPM When set to 1 this avoids instruc tion cache fetches and possible MMU table walk for predicted instructions that may be annullated 24 Reserved field...

Page 72: ...enter debug mode this is configured via DSU AHB trace buffer control register s TE and DF fields see section 33 6 7 The up counter value will increment even if all processors have entered power down...

Page 73: ...LEON4 debug support unit DSU enabled Table 53 asr24 asr26 asr28 asr30 Watchpoint address register s 31 2 1 0 WADDR 31 2 R IF NR 0 0 rw r rw 31 2 Watchpoint address WADDR Address to compare against 1 R...

Page 74: ...struction cache Always reads as zero 20 19 FT scheme FT 01 4 bit checking implemented 18 Reserved for future implementations 17 Separate snoop tags ST Has value 1 16 Reserved 15 Instruction cache flus...

Page 75: ...000 1 0b000 r r rw r r r r r r r r 31 Cache locking CL Set if cache locking is implemented always zeo 30 RESERVED 29 28 Cache replacement policy REPL 00 no replacement policy direct mapped cache 01 le...

Page 76: ...entries is calculated as 2DTLB 24 16 17 16 RESERVED 15 TLB disable TD When set to 1 the TLB will be disabled and each data access will generate an MMU page table walk The TLB should not be disabled on...

Page 77: ...ayouts shown below In the LEON4 the context bits are OR ed with the lower MMU context pointer bits when calculating the address so one can use less context bits to reduce the size alignment requiremen...

Page 78: ...ng the main application This allows software to be portable to both FT and non FT versions of the LEON3 and LEON4 processors 6 11 2 Start up After reset the caches are disabled and the cache control r...

Page 79: ...gister files will be frequently refreshed The similar situation arises for the cache memory In most applications the cache memory is signifi cantly smaller than the full application image and the cach...

Page 80: ...the NS bit is cleared all operations are per formed in standard IEEE compliant mode Following floating point trap types never occur and are therefore never set in the ftt field unimplemented_FPop all...

Page 81: ...following double words contain pending floating point instructions Supervisor software should emulate FPops from the FQ in the same order as they were read from the FQ Note that instructions in the FQ...

Page 82: ...the GRFPU is shown in figure 7 Figure 7 GRFPU Logical View 8 2 Functional description 8 2 1 Floating point number formats GRFPU handles floating point numbers in single or double precision format as...

Page 83: ...ion FSQRTS FSQRTD 000101001 000101010 SP DP SP DP UNF NV NX Square root Conversion operations FITOS FITOD 011000100 011001000 INT SP DP NX Integer to floating point conversion FSTOI FDTOI 011010001 01...

Page 84: ...mented Over flow OF and underflow UF are detected before rounding If an operation underflows the result is flushed to zero GRFPU does not support denormalized numbers or gradual underflow A special Un...

Page 85: ...rts handling of Not a Numbers NaNs as defined in the IEEE 754 standard Opera tions on signaling NaNs SNaNs and invalid operations e g inf inf generate the Invalid exception and deliver QNaN_GEN as res...

Page 86: ...policies LRU least recently used pseudo random and master index The reset value for replacement policy is LRU With the master index replacement policy master 0 would replace way 1 master 1 would repl...

Page 87: ...cachable The cache can also be configured to use the HPROT signal to override the default cachable area An access can only be redefined as non cachable by the HPROT signal See table 65 for informatio...

Page 88: ...r status register After power up the error status register needs to be cleared before any valid data can be read out Table 67 Cache action on detected EDAC error Access Error type Cache line not dirty...

Page 89: ...If the replaced cache line is modified dirty this data is stored in a write buffer and after the requested data is fetched from memory the replaced cache line is written to memory For a non cachable...

Page 90: ...together with the flush command in the Fush set index register instead of writing 0 to the cache enable bit in the cache control register Note that after a processor or any other AHB master has initi...

Page 91: ...nd AHB error on a read access the cache will respond with an AMBA ERROR response For a correctable data error which require a cache line to be re fetched from memory the cache will respond with a AMBA...

Page 92: ...Tag 1 way 3 0x8000C Tag 1 way 4 0x80010 Tag check bits way 0 1 2 3 Read only bit 31 RESERVED bit 30 24 check bits for way 1 bit 23 RESERVED bit 22 16 check bits for way 2 bit 15 RESERVED bit 14 8 chec...

Page 93: ...index is larger than number of ways in the cache 11 8 Locked ways LOCK Number of locked ways 7 6 RESERVED 5 HPROT read hit bypass HPRHB When set a non cacheable and non bufferable read access will byp...

Page 94: ...flushed bit should be set to zero When a way flush is issued the bits in this field will be written to the TAGs for the selected cache way 9 Fetch Line FL If set to 1 data is fetched form memory when...

Page 95: ...EDAC error 7 6 Selects CB data check bits for diagnostic data write 00 use generated check bits 01 use check bits in the data check bit register 10 XOR check bits with the data check bit register 11 u...

Page 96: ...B Check bits which can be selected by the Select check bit field in the error status control register for TAG updates 31 28 27 0 RESERVED CB 0 0 r rw 31 28 RESERVED 27 0 Data Check bits CB Check bits...

Page 97: ...Table 79 0x38 L2CEINJ L2C Error injection register Error injection register 31 16 15 0 RESERVED DEL 0 0 r rw 31 16 RESERVED 15 0 Scrub Delay DEL Delay the scrubber waits before issue the next line sc...

Page 98: ...ed will be placed in the split queue when the split queue is not empty 9 No hit for cache misses NHM When set the unsplited read access for a read miss will not trig the access hit counters 8 Bit erro...

Page 99: ...on When set to 0 the access detecting a un correctable TAG error would generate a AMBA error response When set to 1 this access would not generate an error response This field is only available in sil...

Page 100: ...configuration and two write accesses in non EDAC configuration Each write access can be up to the configured burst length in size The controller will mask the write latency by storing the data into th...

Page 101: ...grammed CAS delay The read cycle is terminated with a PRE CHARGE command no banks are left open between two accesses Write cycles are performed similarly to read cycles with the difference that WRITE...

Page 102: ...ister 2 SDCFG2 register In order for the 2T signaling mode to work the mode register needs to be programmed for length 2 read and length 2 write bursts Therefore after changing the EN2T setting the LO...

Page 103: ...1 0 0 RAS 1 Bank Row 1 RAS 1 Bank Row 1 0 NOP 1 Bank Row 0 RAS 1 Bank Row 2 0 READ 0 Bank Col 1 READ 1 Bank Col 3 0 READ 0 Bank Col 1 0 READ 0 Bank Col 4 0 READ 0 Bank Col 2 1 READ 0 Bank Col 2 5 0 R...

Page 104: ...ble 89 to create a code with 64 data bits and 32 check bits This code can tolerate one nibble error in each of the A B C D groups shown below This means that we can correct 100 of single errors in two...

Page 105: ...are accessed the corresponding access to the address configured in the FTDA register will be performed to the SDRAM and the read data is returned as if it was the contents of the register The access w...

Page 106: ...s all configuration register fields changed with a single register write The data multiplexing control field is set so the top checkbit half replaces the failed part of the data bus The code boundary...

Page 107: ...nd writes The registers are tabulated below Table 94 MMCTRL Registers Offset Register 0x00 SDRAM configuration register 1 SDCFG1 0x04 SDRAM configuration register 2 SDCFG2 0x08 0x1C Reserved 0x20 Mux...

Page 108: ...delay tRCD 25 23 SDRAM banks size BANKSZ Defines the decoded memory size for each SDRAM chip select excluding check bits In half width mode 000 4 Mbyte 001 8 Mbyte 010 16 Mbyte 111 512 Mbyte In full...

Page 109: ...29 16 RESERVED 15 Enable 2T signaling EN2T 14 Double chip select mode DCS 13 Bus parking enable BPARK When this field is set to 1 the controller will start to drive the SDRAM DQ bus eight cycles afte...

Page 110: ...ained an uncorrectable error read only 18 16 Data width DWIDTH 010 32 16 011 64 32 bits 15 12 Back end identifier BEID 0001 SDRAM 11 8 RESERVED 7 5 Data mux control DATAMUX setting this nonzero switch...

Page 111: ...word CBC undefined for code B 15 8 Checkbits for part B of 64 bit data word CBB 7 0 Checkbits for part A of 64 it data word CBA Note that this is a virtual register backed by memory an access to it wi...

Page 112: ...same time an interrupt is gen erated as described hereunder The default threshold is zero and enabled on reset so the first error on the bus will generate an inter rupt The fault tolerant memory contr...

Page 113: ...correctable errors detected during the current scrub run and the number of errors detected during processing of the current count block The size of the count block is a fixed power of two equal or lar...

Page 114: ...rubbing and regeneration modes can be done on the fly during a scrub by modi fying the MODE field in the configuration register The mode change will take effect on the following scrub burst If the add...

Page 115: ...rubber registers AHB address offset Registers 0x00 AHB Status register 0x04 AHB Failing address register 0x08 AHB Error configuration register 0x0C Reserved 0x10 Status register 0x14 Configuration reg...

Page 116: ...hold exceeded SEC Scrubber error counter threshold exceeded Asserted together with NE 10 Scrubber block error counter threshold exceeded SBC Scrubber block error counter threshold exceeded Asserted to...

Page 117: ...e for global uncorrectable error count 13 2 RESERVED 1 Correctable error count threshold enable CECTE Correctable error count threshold enable 0 Uncorrectable error count threshold enable UECTE Uncorr...

Page 118: ...errupt when DONE IRQD Interrupt when task has completed 6 RESERVED 5 Second memory range enable SERA Enables second memory range 4 Loop mode LOOP Restart scrubber when run finishes 3 2 Operation Mode...

Page 119: ...burst size alignment are constant 0 31 22 21 14 13 2 1 0 RECT BECT RESERVED R E C T E B E C T E 0 0 0 0 0 rw rw r rw rw 31 22 Interrupt threshold value for current scrub run correctable error count R...

Page 120: ...Second range high address register 31 5 4 0 RLADDR 0 0b00000 rw r 31 0 Scrubber range low address RLADDR The lowest address in the range to be scrubbed if CONFIG SERA 1 The address bits below the burs...

Page 121: ...ng cores with differing AMBA access size restrictions 12 2 Bridge operation 12 2 1 General The first sub sections below describe the general AHB bridge function The functionality providing access rest...

Page 122: ...xt access is started by performing a SEQ transfer and then holding the bus using BUSY transfers This sequence is repeated until the transfer is ended on the slave side In case of an ERROR response on...

Page 123: ...zero wait states if the bridge is idle this means that performing a write to the idle core does not incur any extra latency However the core must complete the write operation on the master side before...

Page 124: ...the master belongs When the group is known the bridge can propagate or inhibit the access based on the group s attributes or determine the address of the in memory data structures to use for access c...

Page 125: ...increase in page size one bit less of the physical address is used The lowest page is protected by the most significant bit in the bit vector This means that page 0 is protected by the most significa...

Page 126: ...ata for the specified memory range will be cached by the core Bit vector data for accesses made outside the memory range will not be placed in the cache and will instead be fetched for mem ory on each...

Page 127: ...f size 16 28 4096 MiB which is the full 32 bit address space When ITR is set to eight and a page size of 4 KiB is used bits 31 12 of the incoming IO address are trans lated to physical addresses using...

Page 128: ...30 262144 2pgsz 1 2pgsz MiB 7 2048 MiB TMASK 31 524288 2pgsz 2 2pgsz MiB 8 4096 MiB TMASK not used 1048576 2pgsz 4 2pgsz MiB Table 124 IOMMU Page Table Entry IOPTE 31 8 7 6 5 4 3 2 1 0 PPAGE C R BO BS...

Page 129: ...king at the IO address and the System bus plug and play information This operation cannot be done without introducing additional delays when the core is using IOMMU protection The incoming IO address...

Page 130: ...ay only flush part of the TLB and can lead to unexpected behavior When working in IOMMU mode the core can be configured to not store a IOPTE in the TLB if the IOPTE s valid V bit is cleared This behav...

Page 131: ...hould be configured to constrain which registers that can be written from each ASMP block After this initialization is done other parts of the software environment can be brought up As an example cons...

Page 132: ...Master configuration registers Master n configuration register is located at offset 0x40 n 0x4 No 0x80 0xBC Group control registers Group n s control register is located at offset 0x80 n 0x4 Yes prote...

Page 133: ...ks with the first block starting at offset 0x1000 and the last block starting at offset 4 0x1000 19 Configurable Page Size CS Read only 1 the core supports several page sizes and the size is set via t...

Page 134: ...Access Protection Vector Access size CSIZE Read only 2 128 bit 16 byte This field indicates the AMBA access size used when accessing the Access Protection Vector in main memory This is also the cache...

Page 135: ...e the page covered by the IOPTE is accessed If the value of this field is changed a TLB flush must be made to remove any existing IOPTEs from the core s internal buffer Also if this field is set to 0...

Page 136: ...e set address when performing the flush This flush option is only available if the core has support for group set addressing CA field of Capability register 1 is non zero This flush option must only b...

Page 137: ...ied an AMBA access This field is cleared by writing 1 to this position writes of 0 have no effect 0 Translation Error TE The core received an AMBA ERROR response while accessing the bit vec tor or pag...

Page 138: ...aster FMASTER Index of the master that initiated the failed access This field is updated depending on the value of the Control register AU field and the Status register AD field 31 24 23 12 11 5 4 3 0...

Page 139: ...he access 31 30 29 22 21 20 19 18 0 DA RW RESERVED DP TP R SETADDR 0 0 0 0 0 0 NR rw rw r rw rw r rw 31 Diagnostic Access DA When this bit is set to 1 the core will perform a diagnostic operation to t...

Page 140: ...he line When using APV protection then the fetched vector is reversed before it is written in the cache This means that bit 127 of the fetched vector is located in bit 0 of Diagnostic data access regi...

Page 141: ...et 0x100 n 0x4 then the Status register in ASMP register block n is writable Otherwise writes to the Status register in ASMP register block n will be inhibited 16 Mask register access control MC If th...

Page 142: ...register bank interface Note that there is no automatic turning off of the LVDS drivers of disabled or inactive SpaceWire links in this device so this must be managed by the application software See...

Page 143: ...incoming packets with a specific address The RTR RTPMAP registers are not initialized after reset power up For physical addresses this has the effect that the incoming packet is routed to the port th...

Page 144: ...port s data character timer section 13 2 15 the spill if not ready feature for the address section 13 2 10 and the link start on request feature for the output ports section 13 2 13 See table 175 in s...

Page 145: ...the group of ports configured for the packet since the packet should be sent to all ports in the group 13 2 12 Invalid address error An invalid address error occurs under the conditions listed below W...

Page 146: ...R register and the corresponding RTR PTIMER register 4 The port s corresponding RTR PCTRL LS bit has not been set to 1 The auto disconnect feature is only available for the SpaceWire ports since the c...

Page 147: ...nality is basically the same for the configuration port as for the other ports When a command is received the configuration port is the output port of the data transfer and when a reply is sent the co...

Page 148: ...to 1 is called an extended interrupt code and bits 4 0 specify an interrupt num ber between 32 and 63 If bit 5 is set to 0 bits 4 0 specify an interrupt number between 0 and 31 The interrupt codes and...

Page 149: ...that has transmission of interrupt codes or interrupt acknowledgment codes extended interrupt codes enabled RTR PCTRL2 IT and RTR PCTRL2 AT respectively 13 2 18 2Interrupt distribution timers Each in...

Page 150: ...de can be configured to be either level type or edge type Level type means that a new interrupt code will be sent as long as any bit in the RTR PIP register is set Edge type means that a new interrupt...

Page 151: ...is considered valid if the corresponding ISR bit is flipped due to the reception of the code The feature can be enabled individually for each port by setting the corre sponding RTR PCTRL TS bit to 1 A...

Page 152: ...tatus information for the ports are acces sible through the router s configuration port either through RMAP or AMBA AHB see section 13 5 3 13 3 1 Link interface FSM The link interface FSM controls the...

Page 153: ...ered from the data and strobe signals by the PHY module which presents it as a data and data valid signal The receiver is activated as soon as the link interface leaves the error reset state Then afte...

Page 154: ...If a reply was requested it is automatically transmitted back to the source by the RMAP transmitter The AMBA ports are controlled by writing to a set of user registers through the APB interface and a...

Page 155: ...r not a Time Code is forwarded to any other port after it has been sent by an AMBA port depends on the settings explained in 13 2 17 A Time Code that is received by an AMBA port will be stored in the...

Page 156: ...hat neither match the default address register nor the DMA channels address register will be discarded Figure 15 shows a flowchart of the packet reception At least 2 non EOP EEP N Chars needs to be re...

Page 157: ...umber will receive the packet Start Reception Receive 2 bytes rmap enabled defaddr defmask rxaddr defmask Yes Receive 1 byte RMAP command No Yes No Set DMA channel number to 0 Process RMAP command Sep...

Page 158: ...e descriptors should be written to the memory area the receiver descriptor table address register is pointing to Newly added descriptors must always be placed after the previous one written to the are...

Page 159: ...et is spilled depend ing on the value of nospill The receiver can be disabled at any time which will stop packets from being received to this channel If a packet is currently received when the receive...

Page 160: ...eparate entities controlling the transmissions The use of a single channel with multiple controlling entities would cause them to corrupt each other s transmissions A single channel is more efficient...

Page 161: ...s to be done because each time the port encounters a disabled descriptor this register bit is set to 0 Table 148 TXDMA transmit descriptor word 0 address offset 0x0 31 18 17 16 15 14 13 12 11 8 7 0 RE...

Page 162: ...tting a bit in the current descriptor The descriptor table register can be updated with a new table anytime when no transmission is active No transmission is active if the transmit enable bit is zero...

Page 163: ...bes the target implementation 13 4 6 1 Fundamentals of the protocol RMAP is a protocol which is designed to provide remote access via a SpaceWire network to memory mapped resources on a SpaceWire node...

Page 164: ...ied write command the incrementing address bit can be set to any value Non verified writes have no restrictions when the incrementing bit is set to 1 If it is set to 0 the num ber of bytes must be a m...

Page 165: ...in a buffer with more than one entry several commands can be processed before a reply is sent out Data for read replies is read when the reply is transmitted and thus write commands that arrived afte...

Page 166: ...dress do not verify before writ ing no acknowledge Executed normally No restric tions No reply is sent 0 1 1 0 1 0 Write sin gle address do not verify before writ ing send acknowledge Executed normall...

Page 167: ...registers which are 32 bits wide Accesses to this interface are required to be aligned word accesses The result is undefined if this restriction is violated 0 1 1 1 0 1 Write incre menting address ve...

Page 168: ...r several consecutive accesses HTRANS is always NONSEQ in this case while for incrementing accesses it is set to SEQ after the first access This feature is included to support non incrementing reads a...

Page 169: ...port DMA address channels 1 4 RTR AMBADMAADDR 0x34 0x54 0x74 0x94 RESERVED 0x38 0x58 0x78 0x98 RESERVED 0x3C 0x5C 0x7C 0x9C RESERVED 0xA0 AMBA port Distributed interrupt control RTR AMBAINTCTRL 0xA4...

Page 170: ...8 RESERVED 17 RMAP buffer disable RD If set only one RMAP buffer is used This ensures that all RMAP commands will be executed consecutively 16 RMAP Enable RE Enable RMAP target 15 9 RESERVED 8 Tick ou...

Page 171: ...11 9 RESERVED 8 Early EOP EEP EE Set to one when a packet is received with an EOP after the first byte for a non RMAP packet and after the second byte for an RMAP packet 7 Invalid Address IA Set to o...

Page 172: ...AL For each bit set to 1 in the RTR AMBATIME TCMSK the corresponding bit in this field must match the value of the same bit of a received time code in order to that time code to generate and AMBA IRQ...

Page 173: ...ved when this bit is set independent of the SA bit 14 Strip addr SA Remove the addr byte first byte of each packet 13 Enable addr EN Enable separate node address for this channel 12 No spill NS If cle...

Page 174: ...8C RTR AMBADMARXDESC AMBA port DMA receive descriptor table address 31 10 9 3 2 0 DESCBASEADDR DESCSEL RESERVED N R 0x00 0x0 rw rw r 31 10 Descriptor table base address DESCBASEADDR Sets the base addr...

Page 175: ...BA interrupt is generated when an interrupt code is received such that a bit in the RTR AMBAINTRX register is set to 1 even if the bit was already set when the code was received 17 16 RESERVED 15 Hand...

Page 176: ...umber as the bit index This bit gets set to 1 an interrupt acknowledg ment code is received for which the corresponding bit in the RTR AMBAINTMSK0 register is set and either if RTR AMBAINTCTRL AA is s...

Page 177: ...Length fields must contain a value of either 0 or 4 For read modify write commands the Data Length fields must contain a value of either 0 or 8 For write commands the Verify Data Before Write bit in...

Page 178: ...operation performed if the requirements in section 13 5 1 1 are met 0 1 0 0 Invalid No operation performed Error code 0x02 is saved in the RTR PCTRLCFG EC field No reply is sent 0 1 0 1 Invalid No ope...

Page 179: ...ommand is buffered before it is executed a command that contains an error is never exe cuted 1 1 0 1 Write incre menting address verify before writing no reply Write operation performed if the require...

Page 180: ...RMAP command code 0x02 RMAP error code is saved in the RTR PCTRLCFG EC field Reply is sent if the Reply bit in the command s Instruction field was set to 1 7 Invalid Target Logical Address 0x0C RMAP e...

Page 181: ...0x00000000 RESERVED 0x00000004 0x00000030 Routing table port mapping physical addresses 1 12 RTR RTPMAP 0x00000034 0x0000007C RESERVED 0x00000080 0x000003FC Routing table port mapping logical address...

Page 182: ...000E00 0x00000E30 Maximum packet length ports 0 12 RTR MAXPLEN 0x00000E50 0x00000E7C RESERVED 0x00000E84 0x00000E20 Credit counter ports 1 8 RTR CREDCNT 0x00000E24 0x00000FFC RESERVED 0x00001000 RESER...

Page 183: ...e 176 0x00000404 0x00000430 0x00000480 0x000007FC RTR RTACTRL Routing table address control addresses 1 12 and 32 255 31 4 3 2 1 0 RESERVED SR EN PR HD 0x0000000 r rw rw rw rw 31 4 RESERVED 3 Spill if...

Page 184: ...eader deletion is not used when static routing is enabled which means that the first byte of the packet is always sent as well This bit can only be set to 1 if the RTR RTRCFG SR bit is set to 1 Note t...

Page 185: ...erted This bit is self clearing and should not be written with 0 while it is 1 since that could abort the ongoing transmit FIFO reset 6 Receive FIFO spill RS Spills the receive FIFO for this port mean...

Page 186: ...CRC Error HC Set to one if a Header CRC error is detected in an RMAP SpaceWire Plug and Play command received by the configuration port See section 13 5 1 4 for error detection order 25 Protocol ID E...

Page 187: ...therwise this bit is 0 20 Active status AC Set to 1 when a packet arrives at this port and the port has been given access to the routing table Cleared when the packet has been transmitted or spilled 1...

Page 188: ...cation mask SM Defines which bits of a time code distributed interrupt code that must match the value specified in RTR PCTRL2CFG SV in order for an RMAP SpaceWire Plug and Play reply packet to be spil...

Page 189: ...rrupt code transmit enable IT Enables the transmission of interrupt codes on this port If set to 0 no inter rupt codes will be forwarded to this port 9 Interrupt code receive enable IR Enabled the rec...

Page 190: ...h RMAP an RMAP reply will not be sent even if the reply bit in the RMAP commands Instruction field is set to 1 This bit is self clearing 6 Enable extended interrupts EE If set to 0 all distributed int...

Page 191: ...on Table 188 0x00000A10 RTR CFGWE Configuration port write enable 31 1 0 RESERVED WE 0x00000000 1 r rw 31 1 RESERVED 0 Configuration port write enable WE When set to 1 write accesses to the configurat...

Page 192: ...header CRC error protocol ID error packet type error early EOP or early EEP has been detected in the configuration port 3 RMAP error RE Generate an interrupt when an error has been detected in the co...

Page 193: ...When set to 1 a new interrupt code is distributed only when a bit in RTR PIP toggles from 0 to 1 See section 13 2 18 17 Interrupt acknowledgment code to interrupt code timer enable TE If set to 1 the...

Page 194: ...bit has its own timer which is started and reloaded with the value of this field when an interrupt code with the corresponding interrupt number is received or generated by the router See section 13 2...

Page 195: ...a length RM This field specifies the maximum data length in an RMAP read write command that the configuration port can handle The length can be determined according to the formula Length 2 RTR CAP RM...

Page 196: ...SpaceWire Plug and Play Unit Vendor and Product ID field see table 219 25 0 SpaceWire Plug and Play Unit product ID PI Double mapping of the PROD bits from the SpaceWire Plug and Play Unit Vendor and...

Page 197: ...1 255 31 30 29 28 27 20 19 1 0 SR EN PR HD RESERVED PE PD N R 0 N R N R 0x00 N R N R rw rw rw rw r rw rw 31 Spill if not ready SR This bit is a double mapping of the RTR RTACTRL SR bit See table 176...

Page 198: ...e additional status codes described in table 208 Note that it is not possible to access the SpaceWire Plug and Play fields through the AHB slave inter face except for the fields that are double mapped...

Page 199: ...mation Device Identification Owner Address 1 0x00000007 SpaceWire Plug and Play Owner Address 2 RTR PNPOA2 Device Information Device Identification Owner Address 2 0x00000008 SpaceWire Plug and Play D...

Page 200: ...Device Status 31 8 7 0 RESERVED STATUS 0x000000 0x00 r r 31 8 RESERVED 7 0 Device status STATUS Constant value of 0x00 Table 213 0x00000003 RTR PNPACTLNK SpaceWire Plug and Play Active Links 31 9 8 1...

Page 201: ...ID field and Unit Serial Number field are valid 0 invalid 1 valid This bit will be 0 after reset power up Once the Unit Vendor and Product ID field has been written with a non zero value this bit wil...

Page 202: ...r it is writable through RMAP and AHB see section 13 5 3 When this field or the PROD field is written with a non zero value the U bit in the Link Information field is set to 1 15 0 Unit product ID VEN...

Page 203: ...Table 223 0x00008000 RTR PNPPCNT SpaceWire Plug and Play Protocol Count 31 5 4 0 RESERVED PC 0x0000000 0x00 r r 31 5 RESERVED 4 0 Protocol count PC Constant value of 0 indicating that no protocols ca...

Page 204: ...els are Scatter Gather I O and TCP UDP over IPv4 checksum offloading for both receiver and transmitter The system contains two GRETH_GBIT cores The AHB master interfaces are connected to the Mas ter I...

Page 205: ...eing sampled See sec tion 3 1 for further information on bootstrap signals 14 3 Tx DMA interface The transmitter DMA interface is used for transmitting data on an Ethernet network The transmission is...

Page 206: ...on of a packet has finished status is written to the first word in the corresponding descriptor The Underrun Error bit is set if the transmitter RAM was not able to provide data at a suf ficient rate...

Page 207: ...bits are always set to 0 since no transmission has occurred The status bits will be written to the last descriptor for the packet which had MO set to 0 when the transmission has finished No interrupts...

Page 208: ...lticast address not broad cast 25 IP fragment IF Fragmented IP packet detected 24 TCP error TR TCP checksum error detected 23 TCP detected TD TCP packet detected 22 UDP error UR UDP checksum error det...

Page 209: ...after the word con taining the last byte up to the maximum size limit has been written to memory The address word of the descriptor is never touched by the GRETH 14 4 4 Reception with AHB errors If an...

Page 210: ...he PHY status change bit in the status register is set each time an event is detected on this signal If the PHY status interrupt enable bit is set at the time of the event the core will also generate...

Page 211: ...e 229 contains the data to be written If R W is zero the data field is empty in the received packets Table 231 shows the application layer fields of the replies from the EDCL The length field is alway...

Page 212: ...ied for the selected buffer size will lead to dropped packets The behavior is unspecified if sending packets exceeding the maximum allowed size 14 7 Media Independent Interfaces There are several inte...

Page 213: ...GRETH_GBIT registers APB address offset Register 0x0 Control register 0x4 Status Interrupt source register 0x8 MAC Address MSB 0xC MAC Address LSB 0x10 MDIO Control Status 0x14 Transmit descriptor poi...

Page 214: ...speed mode normal transmissions are always used with extension inserted Operation is undefined when set to 1 in other speed modes 8 Gigabit GB 1 sets the current speed mode to 1000 Mbit and when set t...

Page 215: ...rror was encountered in receiver DMA engine Cleared when written with a one Not Reset 3 Transmit successful TI A packet was transmitted without errors Cleared when written with a one Not Reset 2 Recei...

Page 216: ...on as the operation is fin ished and the management link is idle this bit is cleared 2 Linkfail LF When an operation completes BUSY 0 this bit is set if a functional management link was not detected 1...

Page 217: ...of the hash table Table 245 0x24 GRETH_GBIT Hash table lsb register 31 0 Hash table 64 32 NR rw 31 0 Hash table lsb Bits 31downto 0 of the hash table Table 246 0x28 GRETH_GBIT EDCL MAC address MSB 31...

Page 218: ...s compliant with the 2 3 PCI Local Bus Specification 15 2 Configuration The core has configuration registers located both in PCI Configuration Space Compliant with the 2 3 PCI Local Bus Specification...

Page 219: ...llowing registers in the PCI Configuration Space Header For more detailed information regarding each field in these registers please refer to the PCI Local Bus Specifi cation Table 248 GRPCI2 Implemen...

Page 220: ...FBBC Returns zero 22 RESERVED 21 66 MHz Capable 66MHZ NOTE In this implementation this bit has been defined as the status of the PCI_M66EN signal rather than the capability of the core For a 33 MHz de...

Page 221: ...e writable 7 0 Cache Line Size NOT IMPLEMENTED Returns zero Table 253 0x10 0x24 Base Address Registers 31 4 3 2 1 0 Base Address PF Type MS 0 0 0 rw r r r 31 4 Base Address The size of the BAR is dete...

Page 222: ...ndicates the first item in the list of capabilities of the Extended PCI Configu ration Space Value 0x40 Table 255 0x3C Max_Lat Min_Gnt Interrupt Pin and Interrupt Line register 31 24 23 16 15 8 7 0 Ma...

Page 223: ...6 15 8 7 0 RESERVED Length Next Pointer Capability ID 0 0x40 0x00 0x09 r r r r 31 24 RESERVED 23 16 Length Returns 0x40 15 8 Next Pointer Pointer to the next item in the list of capabilites Set to 0x0...

Page 224: ...d time out enable DISEN When set to 1 the target will discard a pending access if no retry of the access is detected during 2 15 PCI clock cycles 0 PCI bus endianess switch ENDIAN 1 defines the PCI bu...

Page 225: ...ut endianess conversion The endianess of the PCI bus is configured via the core specific Extended PCI Configuration Space 15 3 4 PCI configuration cycles Accesses to PCI Configuration Space are not al...

Page 226: ...masked If the master is masked in this register the limit is set to 1 KiB The PCI master does not prefetch data across this address boundary AHB bus As long as a FIFOs are available for writes and dat...

Page 227: ...egister for PCI I O is accessible via the APB slave interface When the IB PCI IO burst bit in the Control register accessible via the APB slave interface is cleared the PCI master does not perform bur...

Page 228: ...target PCI Configuration Read Write Burst and single access to the PCI Configuration Space These accesses are not transferred to the AMBA AHB bus except for the access of the user defined capability...

Page 229: ...15 5 4 PCI to AHB translation Each PCI BAR has translation register mapping register to translate the PCI access to an AMBA AHB address area These mapping registers are accessible via the core specifi...

Page 230: ...t in the DMA control register should be updated The descriptor needs to be aligned to 4 words 0x10 in memory and have the following structure Table 266 GRPCI2 DMA channel descriptor structure Descript...

Page 231: ...43 When the DMA is disabled via the APB interface the channel descriptor is updated to point to the next data descriptor only applies to silicon revision 1 see section 43 The DMA engine will stop whe...

Page 232: ...ster When the Armed bit is set the triggering condition has not occurred The Enable Running bit indicates that the trace buffer still is storing new samples When the delayed stop field is set to a non...

Page 233: ...The deassertion of the PCI reset is synchronized to the PCI clock and delayed 3 clock cycles Reset for the PCI clock domain is generated from the system s SYS_RESETN input as described in section 4 3...

Page 234: ...enabled for Parity error 25 Abort error response ER When set AHB error response is enabled for Master and Target abort 24 Error interrupt EI When set Interrupt is enabled for Master and Target abort...

Page 235: ...d DMA interrupt on the same IRQ signal 01 PCI INTA D and Error interrupt on the same IRQ signal DMA interrupt on IRQ 1 10 PCI INTA D on IRQ IRQ 3 Error interrupt and DMA interrupt on IRQ 11 PCI INTA D...

Page 236: ...FE RESERVED CHIRQ MA TA PE AE DE NUMCH AC TIV E DIS IE EN 1 0 0 0 0 0 0 0 0 0 0 0 0 rw r wc wc wc wc wc wc rw r rw rw rw 31 Safety guard SAFE Needs to be set to 1 for the control fields to be updated...

Page 237: ...When running this register points to the active descriptor 31 0 DMA channel descriptor base address 0 rw 31 0 Base address of the active DMA channel 31 0 PCI BAR to AHB address mapping 0 rw 31 0 32 bi...

Page 238: ...Set when trace buffer is armed started but the trig condition has not occurred 14 Running EN Set when trace buffer is running 13 12 RESERVED 11 4 Trace buffer depth DEPTH Number of buffer entries 2 D...

Page 239: ...7 6 5 4 3 0 RESERVED CBE 3 0 F R A M E I R D Y T R D Y S T O P D E V S E L P A R P E R R S E R R I D S E L R E Q G N T L O C K R S T RES 0 N R N R N R N R N R N R N R N R N R N R N R N R N R N R 0 r r...

Page 240: ...ce PCI control signal state register 31 0 Sampled PCI AD signal N R r 31 0 The state of the PCI AD signal 31 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 RESERVED CBE 3 0 F R A M E I R D Y T R D Y S T O...

Page 241: ...ve passive Bus Moni tors BM s connected There are 5 possible data transfer types on the MIL STD 1553 bus BC to RT transfer receive RT to BC transfer transmit RT to RT transfer Broadcast BC to RTs Broa...

Page 242: ...Each of the BC RT BM parts has a separate set of registers plus there is a small set of shared registers Some of the control register fields for the BC and RT are protected using a key a field in the...

Page 243: ...on the other hand the schedule s timers will be reset When the extsync bit is set in the schedule s next transfer descriptor the core will wait for a positive edge on the external sync input before s...

Page 244: ...e interrupts and stop the schedule Before a transfer triggered interrupt is generated the address to the corresponding descriptor is written into the BC transfer triggered IRQ ring buffer and the BC T...

Page 245: ...is set store the opposite bus instead only if the per RT bus mask is supported in the core See section 16 4 3 for more information 18 Extended intermessage gap GAP If set adds an additional amount of...

Page 246: ...code 011 is issued only when the number of data words match the success case otherwise code 100 is used Error code 011 can be issued for a correctly executed transmit last command or transmit last sta...

Page 247: ...ust be 1 to identify as branch 30 27 Reserved Set to 0 26 Interrupt if condition met IRQC 25 Action ACT What to do if condition is met 0 Suspend schedule 1 Jump 24 Logic mode MODE 0 Or mode any bit se...

Page 248: ...ent When the RT receives a data transfer request it checks in the subaddress table that the request is legal If it is legal the transfer is then performed with DMA to or from the corresponding data bu...

Page 249: ...can not be logged or disabled No Yes 3 00011 Initiate self test No built in action Yes No 21 18 4 00100 Transmitter shutdown The RT will stop responding to commands on the other bus not the bus on wh...

Page 250: ...to indicate invalid pointer R W 0x10 N 0x0C Unused Note The table entries for mode code subaddresses 0 and 31 are never accessed by the core 31 19 18 17 16 15 14 13 12 8 7 6 5 4 0 0 reserved WRAP IGN...

Page 251: ...tting the IGNDV bit in the subaddress table 30 IRQ Enable override IRQEN Log and IRQ after transfer regardless of SA control word settings Can be used for getting an interrupt when nearing the end of...

Page 252: ...an RT is not responding on a subaddress and the BC then commands the same RT again on subaddress 8 or mode code indicator 0 on the same bus This can lead to the second com mand word being interpreted...

Page 253: ...offset Register 0x00 IRQ Register 0x04 IRQ Enable 0x08 0x0F Reserved 0x10 Hardware config register 0x14 0x3F Reserved 0x40 0x7F BC Register area see table 304 0x80 0xBF RT Register area see table 305...

Page 254: ...0 BM Status register 0xC4 BM Control register 0xC8 BM RT Address filter register 0xCC BM RT Subaddress filter register 0xD0 BM RT Mode code filter register 0xD4 BM Log buffer start 0xD8 BM Log buffer...

Page 255: ...to indicate that the core has been modified to run with a single clock 7 0 Codec clock frequency CCFREQ Reserved for future versions of the core to indicate that the core runs at a different codec clo...

Page 256: ...SCHEDULE TRANSFER LIST POINTER 0x00000000 rw 31 0 Read Currently executing if SCST 001 or next transfer to be executed in regular schedule Write Change address If running this will cause a jump after...

Page 257: ...3 0 are constant zero 128 bit 16 byte aligned Table 318 0x6C BCACP GR1553B BC Asynchronous list current slot pointer 31 0 BC TRANSFER SLOT POINTER 0x00000000 r 31 0 Points to the transfer descriptor c...

Page 258: ...1 to enable listening for requests Table 321 0x88 RTBS GR1553B RT Bus status register 31 9 8 7 5 4 3 2 1 0 RESERVED TFDE RESERVED SREQ BUSY SSF DBCA TFLG 0 0 0 0 0 0 0 0 r rw r rw rw rw rw rw 31 9 RE...

Page 259: ...ag bit broadcast ITFB 23 22 Inhibit override inhibit terminal flag ITF 21 20 Initiate self test broadcast ISTB 19 18 Initiate self test IST 17 16 Dynamic bus control DBC 15 14 Transmit BIT word TBW 13...

Page 260: ...3 2 1 0 BMKEY RESERVED WRSTP EXST IMCL UDWL MANL BMEN 0x0000 0 0 0 0 0 0 0 rw r rw rw rw rw rw rw 31 16 Safety key BMKEY If extra safety keys are enabled see KEYEN this field must be 0x1543 for a writ...

Page 261: ...ter shutdown broadcast override selected transmitter shutdown broadcast STSB 17 Selected transmitter shutdown override selected transmitter shutdown STS 16 Transmit last command TLC 15 Transmit status...

Page 262: ...GR1553B BM Log buffer position 31 22 21 0 BM LOG BUFFER POSITION 0x00000000 r rw r 31 0 Pointer to the next position that will be written to in the BM log buffer Only bits 21 3 are settable i e the bu...

Page 263: ...ore To store messages to memory the DMA controller initiates a burst of write accesses on the AMBA AHB bus which are performed by the AHB master When a programmable number of mes sages have been recei...

Page 264: ...tion Version 2 0 Part B except for the overload frame generation Note that there are three different CAN types generally defined 2 0A which considers 29 bit ID messages as an error 2 0B Passive which...

Page 265: ...available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 2 and CanTxRD READ 0 There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 0 and CanTxRD READ 6 There are 2 CAN...

Page 266: ...ister SYNC and SYNC Mask Filter Reg ister MASK registers is successfully transmitted Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus 17 5 5 Straight buffer It...

Page 267: ...before the channel can be re configured safely i e changing address size or read pointer It is also possible to wait for the Tx and TxLoss interrupts described hereafter The channel can be re enabled...

Page 268: ...last CAN message read from the buffer The read pointer operates on number of CAN messages not on absolute or relative addresses The difference between the write and the read pointers is the number of...

Page 269: ...uffer as a straight buffer with a higher granularity than the 1kbyte address boundary limited by the base address CanRxADDR ADDR field While the channel is disabled the write pointer CanRxWR WRITE can...

Page 270: ...ously received message is still being stored A full circular buffer will lead to OR interrupts for any subsequently received messages Note that the last message stored which fills the circular buffer...

Page 271: ...Status Register 0x104 Pending Interrupt Masked Register 0x108 Pending Interrupt Status Register 0x10C Pending Interrupt Register 0x110 Interrupt Mask Register 0x114 Pending Interrupt Clear Register 0...

Page 272: ...n jumps according to the CAN stan dard being in the range 1 to 4 For SAM 0b single the bus is sampled once recommended for high speed buses SAE class C 31 24 23 20 19 16 15 14 12 11 10 9 8 7 6 5 4 3 2...

Page 273: ...e defined according to CAN protocol Note that the AHBErr bit is only set to 1b if an AMBA AHB error occurs while the Can CONF ABORT bit is set to 1b 17 9 3 Control Register CanCTRL Table 342 0x008 Can...

Page 274: ...er CanTxCTRL Table 345 0x200 CanTxCTRL Transmit Channel Control Register Note that if the SINGLE bit is 1b the channel is disabled i e the ENABLE bit is cleared to 0b if the arbitration on the CAN bus...

Page 275: ...condition checking 17 9 9 Transmit Channel Write Register CanTxWR Table 348 0x20C CanTxWR Transmit Channel Write Register The WRITE field is written to in order to initiate a transfer indicating the p...

Page 276: ...s indicates that all messages in the buffer have been transmitted The field is implemented as relative to the buffer base address scaled with the SIZE field 17 9 11 Transmit Channel Interrupt Register...

Page 277: ...is is to simplify wrap around condition checking 17 9 15 Receive Channel Write Register CanRxWR Table 354 0x30C CanRxWR Receive Channel Write Register The field is implemented as relative to the buffe...

Page 278: ...hat a programmed number of messages have been received The field is implemented as relative to the buffer base address scaled with the SIZE field 17 9 18 Receive Channel Mask Register CanRxMASK Table...

Page 279: ...red when it is read or when the Pending Interrupt Masked Register is read Reading the Pending Interrupt Masked Register yields the contents of the Pending Interrupt Register masked with the contents o...

Page 280: ...ion could be caused by communications error as indicated by other interrupts as well 15 RxMiss Message filtered away during reception 14 TxErrCntr Transmission error counter incremented 13 RxErrCntr R...

Page 281: ...TxErrCntr Transmission Error Counter RxErrCntr Reception Error Counter AHBErr AHB interface blocked due to AHB Error when 1b OR Reception Over run when 1b OFF Bus Off mode when 1b PASS Error Passive m...

Page 282: ...s 18 2 2 AHB read transfers When a read transfer is registered on the slave interface the bridge connected to the Processor AHB bus gives a SPLIT response The master that initiated the transfer will b...

Page 283: ...at has received a SPLIT response from the bridge The AMBA specification requires that the locked transfer is handled before the previous transfer which received a SPLIT response is completed The bridg...

Page 284: ...l read burst of same access size as on slave interface the length is the same as the length of the incoming burst The master interface will insert BUSY cycles between the sequential accesses Read burs...

Page 285: ...he bridge is idle this means that performing a write to the idle core does not incur any extra latency However the core must complete the write operation on the master side before it can handle a new...

Page 286: ...OM access Up to two PROM chip select signals are provided for the PROM area PROM_CEN 1 0 The size of the banks can be set in binary steps from 16 KiB to 256 MiB A read access to PROM consists of two d...

Page 287: ...io_addr prom_cen promio_data promio_oen data1 data2 clk D1 D2 A1 A2 Figure 24 Prom consecutive read cyclecs data1 data2 promio_addr prom_cen promio_data promio_oen data2 data clk A1 D2 D1 A2 data1 Fig...

Page 288: ...provide stable address before IO_SN is asserted All accesses are performed as non consecutive accesses as shown in figure 28 The data2 phase is extended when waitstates are added Figure 26 Prom write...

Page 289: ...16 bit memory will generate a burst of two 16 bit reads During writes only the necessary bytes will be writ ten Figure 30 shows an interface example with 8 bit PROM Figure 31 shows an example of a 16...

Page 290: ...performed in burst mode Burst transfers will be generated when the memory controller is accessed using an AHB burst request These includes instruction cache line fills double loads and double stores T...

Page 291: ...data and checkbit area A read access will automatically read the four data bytes individually from the nominal addresses and the EDAC checkbit byte from the top part of the bank Write accesses must on...

Page 292: ...l take at least one additional cycle from when BRDYN is first asserted until it is visible internally In figure 33 one cycle is added to the data2 phase Figure 32 READ cycle with one extra data2 cycle...

Page 293: ...se propagation If BEXCN is 0 then the bus ready enable for the accessed memory area will be disabled and the core will ignore bus ready for the accessed area Bus ready timeout functionality is disable...

Page 294: ...MBA error response if external memory bus timeouts see section 5 10 for information on ERROR response propagation 24 RESERVED 23 20 I O waitstates IO WAITSTATES Sets the number of waitstates during I...

Page 295: ...C diagnostic write bypass WB RESERVED in this device always write to 0 10 EDAC diagnostic read bypass RB RESERVED in this device always write to 0 9 RESERVED 8 PROM EDAC enable PE Enable EDAC checking...

Page 296: ...ns fields to control bus ready timeout Table 368 Memory configuration register 7 31 16 BRDYNCNT 0 rw 15 0 BRDYNRLD 0 rw 31 16 Bus ready count BRDYNCOUNT Counter value If this register is written then...

Page 297: ...will automatically be reloaded with the value of the corresponding timer reload register if the restart bit in the control register is set otherwise it will stop at 1 and reset the enable bit If the i...

Page 298: ...The number of imple mented registers depend on the number of implemented timers Table 369 General Purpose Timer Unit registers APB address offset Register 0x00 Scaler value register 0x04 Scaler reloa...

Page 299: ...l timers will drive the same interrupt line otherwise timer n will drive the first interrupt line assigned to the core n GPTIMER 0 has one ded icated interrupt for each timer GPTIMER unit 1 to 4 have...

Page 300: ...a system is in debug mode 5 Chain CH Chain with preceding timer If set for timer n timer n will be decremented each time when timer n 1 underflows This field is reset to 0 for the watchdog timer It is...

Page 301: ...core s register set is duplicated on 4 KiB address boundar ies In addition to the traditional LEON multiprocessor interrupt controller register interface the core s register interface will also enable...

Page 302: ...llers If the ICF field is 0 the bits in a processor s Interrupt Force register can only be set from the controller to which the processor is assigned 21 2 2 Interrupt prioritization The interrupt cont...

Page 303: ...pt controller and the interrupt pending and mask registers have been extended to 32 bits Since the processor only has 15 interrupt levels 1 15 the extended interrupts will generate one of the regular...

Page 304: ...ware must then clear the S1 and S2 fields for a new timestamp to be taken If Keep Stamp is disabled KS field not set the controller will update the Interrupt Assertion Timestamp Register every time th...

Page 305: ...The Interrupt map registers are available start ing at offset 0x300 from the interrupt controller s base address The interrupt map registers contain one field for each bus interrupt line in the system...

Page 306: ...e 378 Interrupt Controller registers APB address offset Register 0x000 Interrupt level register 0x004 Interrupt pending register 0x008 Interrupt force register NCPU 0 0x00C Interrupt clear register 0x...

Page 307: ...egister silicon revision 1 0x208 Processor 2 reset start address register silicon revision 0 Processor 2 boot address register silicon revision 1 0x20C Processor 3 reset start address register silicon...

Page 308: ...ter 31 16 15 1 0 EIP 31 16 IP 15 1 R 0 0 0 rw rw r 31 16 Extended Interrupt Pending n EIP n Interrupt pending for interrupt n 15 1 Interrupt Pending n IP n Interrupt pending for interrupt n 0 Reserved...

Page 309: ...o 0 in GR740 silicon revision 0 and set to 1 in GR740 silicon revision 1 25 20 RESERVED 19 16 Extended IRQ EIRQ Interrupt number 1 15 used for extended interrupts Fixed to 0 if extended interrupts are...

Page 310: ...the controller s Interrupt Pending Register Bit n in the watchdog input is connected to GPTIMER n 1 s timer 4 tick output 31 28 27 2 1 0 NCTRL RESERVED ICF L 0x3 0 0 0 r r rw rw 31 28 Number of intern...

Page 311: ...1 16 IM15 1 R 0 0 R rw rw r 31 16 Extended Interrupt Mask n EIC n Interrupt mask for extended interrupts 15 1 Interrupt Mask n IM n If IM n 0 then interrupt n is masked otherwise it is enabled 0 RESER...

Page 312: ...of timestamp register sets TSTAMP The number of available timestamp register sets 26 Assertion Stamped S1 Set to 1 when the assertion of the selected line has received a timestamp This bit is cleared...

Page 313: ...1 31 0 TACKNOWLEDGE 0 r 31 0 The time value used for stamping is the DSU timer which is also available as the processor internal up counter Table 396 0x200 n 4 PRSTADDRn Processor n reset start addres...

Page 314: ...ntly idle in power down error or debug mode if a processor is running then the write to its bit in this field will be ignored Multiple bits in this register may be set with one write but the register...

Page 315: ...0x300 4 n specifies the mapping for interrupt lines 4 n to 4 n 3 The bus interrupt line 4 n x will be mapped to the interrupt controller interrupt line specified by the value of IRQMAP n 4 x The inter...

Page 316: ...s can be read out from the I O port data register The output enable is controlled by the I O port direction register A 1 in a bit position will enable the output buffer for the correspond ing I O line...

Page 317: ...nterrupt map register 0 0x24 Interrupt map register 1 0x28 Interrupt map register 2 0x2C Interrupt map register 3 0x30 0x3C Reserved 0x40 Interrupt available register 0x44 Interrupt flag register 0x48...

Page 318: ...te This field has range 15 0 for the first GPIO port GRGPIO0 and range 21 0 for the second GPIO port GRGPIO1 Reset value depends on state of external signals 31 nlin nlin 1 0 RESERVED DATA 0 0 r rw 31...

Page 319: ...pt polarity register 22 3 6 Interrupt edge register Table 406 0x14 IEDGE Interrupt edge register 31 16 15 0 RESERVED MASK 0 0 r rw 31 16 RESERVED 15 0 Interrupt mask MASK 0 interrupt masked 1 intrrupt...

Page 320: ...in this implemen tation 12 8 Interrupt generation setting IRQGEN Set to 4 to signify that the core has Interrupt map registers allowing software to dynamically map which lines that should drive inter...

Page 321: ...has been generated and remain set until cleared by writing to this register 31 16 15 0 RESERVED PULSE 0 0 r rw 31 16 RESERVED 15 0 PULSE If PULSE n is set to 1 then OUTPUT register bit n will be inve...

Page 322: ...al OR AND XOR registers 31 nlin nlin 1 0 RESERVED DATA 0 0 r w 31 nlin RESERVED nlin 1 0 The logical OR AND XOR registers will update the corresponding register see table 400 accord ing to New value O...

Page 323: ...the transmitter FIFO to the transmitter shift register and converted to a serial stream on the transmitter serial output pin The core automatically sends a start bit followed by eight data bits an opt...

Page 324: ...value is taken into account effectively forming a low pass filter with a cut off frequency of 1 8 system clock The receiver also has a FIFO which is identical to the one in the transmitter During rec...

Page 325: ...interrupts are generated when receiver FIFO interrupts are enabled the receiver is enabled and the FIFO is half full The interrupt signal is continuously driven high as long as the receiver FIFO is h...

Page 326: ...shows the number of data frames in the receiver FIFO 25 20 Transmitter FIFO count TCNT shows the number of data frames in the transmitter FIFO 10 Receiver FIFO full RF indicates that the Receiver FIFO...

Page 327: ...enable BI When set an interrupt will be generated each time a break character is received See section 16 6 for more details 11 FIFO debug mode enable DB when set it is possible to read and write the F...

Page 328: ...it will monitor the SPISEL signal to detect collisions with other masters if SPI_SEL is activated the master will be disabled During a transmission on the SPI bus data is either changed or read at a...

Page 329: ...word back to the slave The data line transitions depending on the clock polarity and clock phase in the same manner as in SPI mode The aforementioned slave delay of the SPI_MISO signal in SPI mode wi...

Page 330: ...3 wire mode the core will first listen to the SPI_MOSI line and when a word has been transferred drive the response on the SPI_MOSI line If the core is selected when the transmit queue is empty it wi...

Page 331: ...that the core can be configured to ignore SPI_SEL by setting the IGSEL field in the Mode register 24 3 Registers The core is programmed through registers mapped into APB address space Table 419 SPI co...

Page 332: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R L O O P C P O L C P H A D I V 1 6 R E V M S E N LEN PM T W E N A S E L F A C T O D CG A S E L D E L T A C T T O I G S E L C I T E R 0 0 0 0 0 0 0 0 0 0 0...

Page 333: ...eld 12 Open drain mode OD If this bit is set to 0 all pins are configured for operation in normal mode If this bit is set to 1 all pins are set to open drain mode The pins driven from the slave select...

Page 334: ...receives new data The core continues communicating over the SPI bus but discards the new data This bit is cleared by writ ing 1 writes of 0 have no effect 11 Underrun UN This bit is only set when the...

Page 335: ...rate an interrupt when the UN bit in the Event register transitions from 0 to 1 10 Multiple master error enable MMEE When this bit is set the core will generate an interrupt when the MME bit in the Ev...

Page 336: ...uld be written with its most significant bit at bit 31 31 0 RDATA 0 r 31 0 Receive data RDATA This register contains valid receive data when the Not empty NE bit of the Event register is set The place...

Page 337: ...ESERVED A S L V S E L 0 0 r rw 31 2 RESERVED 1 0 Automatic Slave select ASLVSEL The core s slave select signals are assigned from this register when the core is about to perform a transfer and the ASE...

Page 338: ...the core through software to make sure it does not initialize any AHB accesses 2 Write a 1 to the corresponding bit in the unlock register 3 Write a 0 to the corresponding bit in the clock enable reg...

Page 339: ...n processor core connected to the FPU has floating point disabled or when the processor core is in power down mode Processor FPU clock gating can be disabled by writing 0x000F000F to the CPU FPU overr...

Page 340: ...enable and core reset regis ters can only be written when the corresponding bit in this field is 1 31 11 10 0 RESERVED ENABLE 0 r rw 31 11 RESERVED 10 0 Cock enable ENABLE A 1 in a bit location will...

Page 341: ...ESERVED FOVERRIDE RESERVED OVERRIDE 0 0 0 0 r rw r rw 31 20 RESERVED 19 16 Override FPU clock gating FOVERRIDE If bit n of this field is set to 1 then the clock for FPU n will be active regardless of...

Page 342: ...ta cache read miss 0x09 Data MMU TLB miss 0x0A Data cache hold 0x0B Data MMU hold 0x10 Data write buffer hold 0x11 Total instruction count 0x12 Integer instructions 0x13 Floating point unit instructio...

Page 343: ...s error denied external event 9 CPU AHBM field must be set to 0 0x6A IOMMU access OK external event 10 CPU AHBM field must be set to 0 0x6B IOMMU access passthrough external event 11 CPU AHBM field mu...

Page 344: ...ics unit Master indexes are listed in section 2 5 26 2 Multiple APB interfaces The core has two AMBA APB interfaces the first is connected via the Processor AHB bus and the second is connected via the...

Page 345: ...Counter 14 value register 0x3C Counter 15 value register 0x40 0x7C Reserved 0x80 Counter 0 control register 0x84 Counter 1 control register 0x88 Counter 2 control register 0x8C Counter 3 control regis...

Page 346: ...h register 0x140 0x17C Reserved 0x180 Timestamp register 0x184 0x1FC Reserved 31 0 CVAL NR rw 31 0 Counter value CVAL This register holds the current value of the counter If the core has been implemen...

Page 347: ...um duration CD If this bit is set to 1 the core will save the maximum time the selected event has been at the level specified by the EL field This also means that the counter will be reset when the ev...

Page 348: ...control register field CDis 0 then the value displayed by this register is the latched saved counter value The counter value is saved whenever a write access is made to the core in address range 0x100...

Page 349: ...the same as for an AHB error response The only difference is that the Correctable Error CE bit in the status register is set to one when a correctable error is detected When the CE bit is set the int...

Page 350: ...Filter Write FW This bit needs to be set to 1 during a write operation for CF and AF fields to be updated in the same write operation Always reads as zero This field is only available in GR740 silico...

Page 351: ...er is propagated to other peripherals in the design The reset value of the register is taken from the GPIO signals and from the bootstrap signals PLL_IGNLOCK PCIMODE_ENABLE MEM_CLKSEL and MEM_IFWIDTH...

Page 352: ...LL_BYPASS 1 bootstrap signal B6 The value in this register can be written but the changed value does not affect system operation This field is only available in GR740 silicon revision 1 20 Reset value...

Page 353: ...every 12th sensor clock cycle sensor clock frequency is determined by the system clock fre quency and the control register DIV field When the status register field UPD is set to 1 then the result of...

Page 354: ...emperature sensor will be clocked with the frequency System clock frequency 2 DIV Allowable input clock frequencies for the temperature sensor is 125 kHz to 250 kHz A suitable DIV value can be calcula...

Page 355: ...ite operation This field is immediately reset to 0 to prevent accidental writes to the MAX and MIN fields 9 Updated UPD This bit is set to 1 whenever a new DATA value is read from the sensor The bit i...

Page 356: ...described in section 3 3 1 30 2 2 LVDS pad enable control The LVDS enable control registers allow to turn off unused LVDS output drivers for the spacewire links as well as the differential memory clo...

Page 357: ...lockdown reg ister is not reset when the PLL is reconfigured but only when the external reset signal is asserted Table 452 Groups for pad drive strength control Group Description Pins 0 SDRAM outgoing...

Page 358: ...nly 0x18 Drive strength configuration register 1 0x1C Drive strength configuration register 2 0x20 Config lockdown register 0x24 0xFF Reserved 31 22 21 0 RESERVED FTMEN 0 r rw 31 22 RESERVED 21 0 Pinm...

Page 359: ...abled 0 disabled 16 Enable differential SDRAM clock output DMEM 1 enabled 0 disabled 15 8 RESERVED 7 0 Enable LVDS output drivers for SPW links 7 0 SPWOE 1 enabled 0 disabled 31 19 28 27 26 18 17 9 8...

Page 360: ...er 31 19 28 27 26 18 17 9 8 0 RESERVED SWTAG SPWPLLCFG MEMPLLCFG SYSPLLCFG 0 0b000010000 0b000001010 0b000010101 r r r r r 31 29 RESERVED 28 27 Software tag SWTAG Can be used freely as tag data 26 18...

Page 361: ...ive strength setting for output group 2 S2 3 2 Drive strength setting for output group 1 S1 1 0 Drive strength setting for output group 0 S0 Table 461 0x1C DRVSTR2 Drive strength configuration registe...

Page 362: ...23 16 15 8 7 0 RESERVED PERMANENT RESERVED REVOCABLE 0 0 0 0 r rw r rw 31 24 RESERVED 23 16 Permanent lock bit mask PERMANENT Bit N for register at offset 4 N 1 locked 0 unlocked Bits that are set to...

Page 363: ...by means of an RMAP write command carrying a CCSDS Time Code time message The synchronization event is signaled by means of transferring a SpaceWire Time Code The transfer of the SpaceWire Time Code i...

Page 364: ...coarse and fine time implemented in this core can be obtained by reading the DPF bits of Datation Preamble Field register The coarse time code elements are a count of the number of seconds elapsed fr...

Page 365: ...o obtained for this core s current implementation consist of Coarse time width 32 Fine time width 24 and Frequency synthesizer width of 30 To calcu late for other frequencies and configuration refer t...

Page 366: ...performed The MAPPING bits in Configuration 0 register determines the interval between SpaceWire Time Code transmissions which is explained in detail in the section below The target time must be conf...

Page 367: ...fine time implemented which gives the total local ET counter coarse fine width The current implementation has 32 bit coarse and 24 bit fine time then it is enough to access the first two Datation Elap...

Page 368: ...nterrupts only in silicon revision 1 The distributed interrupt transmission from initiator which is the origin for latency calculation is controlled by a mask register STM available in Configuration 3...

Page 369: ...t is driven high for a clock period The EDS bit in Status Register 0 will go high when the condi tion matches and cleared when the latched elapsed time is read The purpose of this status register is t...

Page 370: ...e Codes and the Time code position mapped in the target Elapsed Time is compared if they match the bits available after the compared bits are made zero if the local time map is less than one External...

Page 371: ...Code and Preamble Field Tx 0x084 Time Stamp Elapsed Time 0 Tx 0x088 Time Stamp Elapsed Time 1 Tx 0x08C Time Stamp Elapsed Time 2 Tx 0x090 Time Stamp Elapsed Time 3 Tx 0X094 Time Stamp Elapsed Time 4 T...

Page 372: ...ernal Datation 0 Elapsed Time 1 0x11C External Datation 0 Elapsed Time 2 0x120 External Datation 0 Elapsed Time 3 0x124 External Datation 0 Elapsed Time 4 0x128 RESERVED 0x12C RESERVED 0x130 0x14F Ext...

Page 373: ...the Elapsed Time with the contents of the command field register Note Only available in silicon revision 1 16 Latency Enable LE To calculate latency between an initiator and target this bit must be e...

Page 374: ...and Preamble Field Tx register Value all bits zero will send Distributed interrupts at all SpaceWire Time Codes irrespective of any values in TSTC register Value all ones will send Distributed interr...

Page 375: ...lculated from Preamble field of Command Register 15 14 RESERVED 13 8 Coarse Width CW Coarse width of command CCSDS Time Code received calculated from Pre amble field of Command Register 7 4 RESERVED 3...

Page 376: ...ch the received SpaceWire Time code for time qualification 15 0 Command Preamble Field CPF The number of coarse and fine time available in Command Elapsed Time registers should be mentioned in this fi...

Page 377: ...his Preamble Field Table 482 0x044 DET0 Datation Elapsed Time 0 31 0 DET0 0 r 31 0 Datation Elapsed Time 0 DET0 CCSDS Time Code value 0 to 31 of local ET counter value Table 483 0x048 DET1 Datation El...

Page 378: ...488 0x064 TR0 Time Stamp Elapsed Time 0 Rx 31 0 TR0 0 r 31 0 Time Stamp Elapsed Time 0 Rx TR0 Time stamped local ET value 0 To 31 when distributed interrupt received Table 489 0x068 TR1 Time Stamp El...

Page 379: ...e mask for this matching is available in con figuration register 3 only for initiator 23 16 RESERVED 15 0 Time stamp Preamble Field TTPF The number of coarse and fine time implemented can be obtained...

Page 380: ...F Latency Preamble Field 31 16 15 0 RESERVED LPF 0 0x2f00 r r 31 16 RESERVED 15 0 Latency Preamble Field LPF The number of coarse and fine time implemented can be obtained from this Preamble Field onl...

Page 381: ...re Time Code received Interrupt Enable NCTCE Note Only available in silicon revision 1 18 11 RESERVED 10 Set ET External Interrupt Enable SETE Note Only available in silicon revision 1 9 External Data...

Page 382: ...l Datation Interrupt 3 EDI3 Generated when conditions for External Datation 3 is matched 8 External Datation Interrupt 2 EDI2 Generated when conditions for External Datation 2 is matched 7 External Da...

Page 383: ...ture missing SpaceWire Time Code only for target The INSYNC bit in the Status 0 register will disable itself when an expected SpaceWire Time Code is not arrived after the delay mentioned in this regis...

Page 384: ...Datation 0 Elapsed Time 0 31 0 ED0ET0 0 r 31 0 External Datation Elapsed Time 0 ED0ET0 Latched CCSDS Time Code value 0 to 31 of local ET counter Table 512 0x118 ED0ET1 External Datation 0 Elapsed Tim...

Page 385: ...mally translated to single transfers with the same AHB address and control signals on the master side however read com bining can translate one access into several smaller accesses Translation of burs...

Page 386: ...e table below Read and write combining is disabled for accesses to the area 0xF0000000 0xFFFFFFFF to prevent accesses wider than 32 bits to register areas Table 516 Read and write combining Access on...

Page 387: ...the core has not transitioned into its idle state pending the completion of an earlier access the delay suffered by an access be longer than what is shown in the tables in this section Since the core...

Page 388: ...ritexx 2 0 0 Burst writexx 2 burst length 0 0 x A prefetch operation ends at the address boundary defined by the prefetch buffer s size xx The core implements posted writes the number of cycles taken...

Page 389: ...ers can be accessed at any time while the processor registers caches and trace buffer can only be accessed when the processor has entered debug mode In debug mode the processor pipeline is held and th...

Page 390: ...forwarded to the IU which performs access with ASI equal to value in the DSU ASI register and address consisting of 20 LSB bits of the original address 33 3 AHB Trace Buffer The AHB trace buffer cons...

Page 391: ...ead write and address range so that accesses that correspond to the specified mask are not written into the trace buffer Address range masking is done using the second AHB breakpoint register set The...

Page 392: ...bus after reception of a SPLIT response The core will only keep track of one master at a time This means that when a SPLIT response is detected the core will save the master index This event will then...

Page 393: ...0xFF do not cause operations on the on chip bus and can be used to implement software trace points Table 523 DSU memory map Address offset Register 0x000000 DSU control register 0x000008 Time tag coun...

Page 394: ...only 0x301000 0x30107C FPU register file 0x400000 Y register 0x400004 PSR register 0x400008 WIM register 0x40000C TBR register 0x400010 PC register 0x400014 NPC register 0x400018 FSR register 0x40001C...

Page 395: ...et will force the processor into debug mode on all except the follow ing traps priviledged_instruction fpu_disabled window_overflow window_underflow asynchro nous_interrupt ticc_trap BZ is reset to th...

Page 396: ...me tag counter register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMETAG 0 rw 31 0 DSU Time Tag Value TIMETAG Table 526 0x000020 BRSS DSU break and single...

Page 397: ...the ASI diagnostic access register is used as ASI while the address is supplied from the DSU memory area when per forming an access at offset 0x700000 Table 528 0x400020 DTR DSU trap register 31 30 2...

Page 398: ...s made This means that setting this bit to 1 will cause the values in the trace buffer s sample regis ters to be written into the trace buffer and new values will be sampled into the registers This bi...

Page 399: ...ld applies to AHB breakpoint 2 and bit 8 applies to AHB breakpoint 1 If the BPF bit for a breakpoint is set to 1 then the breakpoint will not trigger unless the access also passes through the filter T...

Page 400: ...e set Table 534 0x000050 0x000058 ATBBA AHB trace buffer break address registers 31 2 1 0 BADDR 31 2 RES NR 0 rw r 31 2 Break point address BADDR Bits 31 2 of breakpoint address 1 0 RESERVED Table 535...

Page 401: ...derflow without generat ing a processor break In this mode the counter can be periodically polled and statistics can be formed on CPI clocks per instructions In non profiling mode PE 0 the processor w...

Page 402: ...watchpoints have one extra cycle of latency compared to a AHB breakpoint due to this pipelining Table 537 0x000080 AHBWPC AHB watchpoint control register 31 7 6 5 4 3 2 1 0 RESERVED IN CP EN R IN CP...

Page 403: ...96 n 32 NR rw 31 0 AHB watchpoint data DATA Specifies the data pattern of one word for an AHB watchpoint The lower part of the register address specifies with part of the bus that the register value...

Page 404: ...31 28 Trace filter configuration TFILT See table 522 27 9 RESERVED 15 0 Instruction trace buffer pointer ITPOINTER Indicates the next line of the instruction trace buffer to be written Table 541 0x110...

Page 405: ...and data register fol lowed by shifting in write data into the data register Sequential transfers can be performed by shifting in command and address for the transfer start address and shifting in SEQ...

Page 406: ...the host can repeat the read of the data register until bit 32 is set to 1 signal ing that the data is valid and that the AMBAAHB access has completed It should be noted that while bit 32 returns 0 n...

Page 407: ...g AHB bus be gated off when the Debug AHB bus is disabled via the external DSU_EN signal 35 2 Operation 35 2 1 Overview The main sub blocks of the core are the link interface the RMAP target and the A...

Page 408: ...hem When transmitting packets the address and protocol ID fields must be included in the buffers from where data is fetched They are not automatically added by the core Figure 47 shows the packet type...

Page 409: ...his is done because one usually wants to run the SpaceWire link on a different frequency than the host system clock The core has a separate clock input which is used to generate the transmitter clock...

Page 410: ...ode is considered to be a Time Code If Time Code reception is enabled CTRL TR bit set to 1 then the received time value is stored in the TC TIMECNT field If the received time value equals TC TIMECNT 1...

Page 411: ...ed for a packet to be stored to the DMA channel unless the promiscuous mode is enabled in which case 1 N Char is enough If it is an RMAP packet with hardware RMAP enabled 3 N Chars are needed since th...

Page 412: ...command No Yes No Set DMA channel number to 0 Process RMAP command Separate addressing No Yes dma n addr rxaddr dma n mask Channel enabled Increment channel number and pid 1 and defaddr defmask rxadd...

Page 413: ...layout can be found in the tables below The descriptors should be written to the memory area pointed to by the receiver descriptor table address register When new descriptors are added they must alwa...

Page 414: ...packets from being received to this channel If a packet is currently received when the receiver is disabled the reception will still be finished The rxdescav bit can also be cleared at any time It wil...

Page 415: ...ncluding the next EEP EOP and then the currently active channel is disabled and the receiver enters the idle state A bit in the channels control status register is set to indicate this condition 35 5...

Page 416: ...4 The dif ferent fields of the descriptor together with the memory offsets are shown in the tables below The HC bit should be set if RMAP CRC should be calculated and inserted for the header field and...

Page 417: ...le transmitter descriptor When all control fields address length wrap and crc are set this bit should be set While the bit is set the descriptor should not be touched since this might corrupt the tran...

Page 418: ...DMA engine was in when the AHB error occurred If the descriptor was being read the packet transmission had not been started yet and no more actions need to be taken If the AHB error occurs during pac...

Page 419: ...ID which are always dumped to the DMA channel The RMAP receiver processes commands If they are correct and accepted the operation is performed on the AHB bus and a reply is formatted If an acknowledg...

Page 420: ...reads have the same alignment restrictions as non verified writes Note that the Authorization failure error code will be sent in the reply if a violation was detected even if the length field was zer...

Page 421: ...e increment ing address Executed normally If length is not one of the allowed rmw val ues nothing is done and error code is set to 11 If the length was correct alignment restric tions are checked next...

Page 422: ...is sent 0 1 1 1 0 1 Write incre menting address ver ify before writing no acknowledge Executed normally Length must be 4 or less Otherwise nothing is done Same alignment restric tions apply as for rm...

Page 423: ...and word HSIZE 0x000 0x001 0x010 Byte and halfword accesses are always NONSEQ The burst length will be half the AHB FIFO size except for the last transfer for a packet which might be smaller Shorter...

Page 424: ...RVED 13 Transmitter enable lock control TL Enables disables the transmitter enable lock functionality described by the DMACTRL TL bit 0 Disabled 1 Enabled 12 Time code control flag filter TF When set...

Page 425: ...urred Cleared when written with a one 2 Escape Error ER An escape error has occurred Cleared when written with a one 1 Credit Error CE A credit has occurred Cleared when written with a one 0 Tick Out...

Page 426: ...0x00 r rw rw 31 8 RESERVED 7 6 Time control flags TCTRL The current value of the time control flags Sent with time code resulting from a tick in Received control flags are also stored in this register...

Page 427: ...eared packets will be discarded when a packet is arriving and there are no active descrip tors If set the GRSPW will wait for a descriptor to be activated 11 Rx descriptors available RD Set to one to...

Page 428: ...2 0x2C SPW2 DMARXDESC DMA receiver descriptor table address channel 1 31 10 9 3 2 0 DESCBASEADDR DESCSEL RESERVED N R 0x00 0x0 rw rw r 31 10 Descriptor table base address DESCBASEADDR Sets the base ad...

Page 429: ...y clearing the DF bit or by setting the TE bit in the DSU AHB trace buffer control register see section 33 6 7 Note that when the processors enter debug mode and stop execution DMA traffic may still b...

Page 430: ...AHB slave inputs and slave has asserted HREADY nseq HTRANS NONSEQ Active when HTRANS NONSEQ is driven on the AHB slave inputs and slave has asserted HREADY seq HTRANS SEQ Active when HTRANS SEQUENTIA...

Page 431: ...ounter Filter PF If this bit is set to 1 the cores performance counter statistical outputs will be filtered using the same filter settings as used for the trace buffer If a filter inhibits a write to...

Page 432: ...ffer index register indicates the address of the next 128 bit line to be written Table 568 0x000004 INDEX Trace buffer index register 31 11 10 4 3 0 RESERVED INDEX RESERVED 0 NR 0 r rw r 31 11 RESERVE...

Page 433: ...lter register The master slave filter register allows filtering out specified master and slaves from the trace This register can only be assigned if the trace buffer has been implemented with support...

Page 434: ...ace buffer is frozen A mask register is associated with each breakpoint allowing breaking on a block of addresses Only address bits with the corresponding mask bit set to 1 are compared during break p...

Page 435: ...with a size of 1 4096 MiB A specific I O area is also decoded where slaves can occupy 256 byte 1 MiB Access to unused addresses will cause an AHB error response See the AMBA ERROR propagation descrip...

Page 436: ...19 16 15 4 3 0 Identification Register 00 10 9 HADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 Bank Address Registers USER DEFINED...

Page 437: ...d areas will be ignored while reads from unassigned areas will return an arbitrary value AHB error responses will never be generated 38 2 2 Plug play information The plug play information is mapped on...

Page 438: ...mV with a maximum duration of 3 ns can be tolerated Table 573 Absolute maximum DC ratings Parameter Abs Max Unit VDD12 relative to GND 1 8 V VDDPLLA relative to VSSPLLA 1 8 V VDDPLLD relative to VSSPL...

Page 439: ...le 575 Input and output DC characteristics Parameter Symbol Conditions Minimum Typical Maximum Unit Input leakage current LVCMOS Ileak 10 10 uA Input capacitance LVCMOS Cin At package pin 35 pF Schmit...

Page 440: ...d Natural power down stopping the supply of current to all power rails on board level simultaneously and then letting the capacitances of the supply rails discharge at their natural rate The I Os shou...

Page 441: ...elevant for the system An IBIS model of the drivers can be provided to aid in this process 39 5 2 Clocks Table 579 summarizes required recommended conditions for some of the design input clocks that c...

Page 442: ...LK duty cycle 20 50 80 6 ETH _RXCLK frequency feth_rxclk 25 25 or 125 125 MHz ETH _RXCLK duty cycle 40 50 60 6 GR1553_CLK frequency fgr1553_clk 19 999 20 20 001 MHz GR1553_CLK duty cycle 20 50 80 6 GR...

Page 443: ...time rising sys_resetn 100000 ns Notes 1 PLL is in power down as long as sys_resetn is held low Unused PLLs for selected configuration are permanently in power down and their corresponding lock signa...

Page 444: ...data output delay rising mem_clk_in edge 3 12 13 3 ns tSDRAM2 data clock to data tri state delay rising mem_clk_in edge 0 1 30 0 2 ns tSDRAM3 data input to clock setup rising mem_clk_in edge 2 76 ns...

Page 445: ...ed by static timing analysis and is not tested 3 The break and dsu_en signals are re synchronized internally These signals do not have to meet any setup or hold requirements As the dsu_en signal contr...

Page 446: ...0GMII transmitter clock to output delay rising GMII clock edge 2 58 10 92 ns tETH1MII GMII_ETH0 input to receiver clock hold ETH0 4 rising RX clock edge 1 84 ns tETH2MII GMII_ETH0 input to receiver cl...

Page 447: ...erated MDC clock frequency is set using a scaler register in the IP core Table 586 Timing parameters Name Parameter Reference edge Min Max Unit tMDIO0 MDIO clock to output delay rising clk edge where...

Page 448: ...data bit period 2 5 2 ns tSPW5 input data bit period 2 5 2 ns tSPW6 data strobe input edge separa tion 2 0 2 3 ns tSPW7 data strobe output skew 0 4 0 4 3 ns 1 Internal SpaceWire clock generated from...

Page 449: ...clock to output delay not applicable tSPWD2 input to clock hold not applicable tSPWD3 input to clock setup not applicable tSPWD4 output data bit period 20 ns tSPWD5 input data bit period 20 ns tSPWD6...

Page 450: ...hold rising pci_clk edge 1 03 ns tPCI2 input to clock setup rising pci_clk edge 6 44 ns tPCI3 clock to output delay rising pci_clk edge 3 05 17 91 ns tPCI4 input to clock hold rising pci_clk edge 1 03...

Page 451: ...ax Unit t1553BRM0 clock to data output delay rising gr1553_clk edge 0 1 40 2 ns t1553BRM1 data input to clock setup rising gr1553_clk edge 3 3 ns t1553BRM2 data input from clock hold rising gr1553_clk...

Page 452: ...n in figures 67 and 68 and are defined in table 591 Figure 67 Timing waveforms PROM accesses tFTMCTRL0 promio_addr internal sys_clk tFTMCTRL1 promio_data output promio_data input prom_cen tFTMCTRL3 tF...

Page 453: ...6 clock to output delay rising clk edge 1 0 2 40 3 ns tFTMCTRL7 data input to clock setup rising clk edge 1 0 2 ns tFTMCTRL8 data input from clock hold rising clk edge 1 ns tFTMCTRL9 input to clock se...

Page 454: ...timing analysis not tested Table 593 Timing parameters Name Parameter Reference edge Min Max Unit tGRGPIO0 clock to output delay rising clk edge 0 1 40 2 ns tGRGPIO1 clock to non tri state delay risin...

Page 455: ...T0 clock to output delay rising clk edge 0 1 40 2 ns tAPBUART1 input to clock hold rising clk edge 3 ns tAPBUART2 input to clock setup rising clk edge 3 ns 1 Guaranteed by design not tested 2 Verified...

Page 456: ...e delay rising clk edge 0 1 40 2 ns tSPICTRL3 input to clock hold rising clk edge 3 ns tSPICTRL4 input to clock setup rising clk edge 3 ns 1 Guaranteed by design not tested 2 Verified by static timing...

Page 457: ...t delay rising clk edge 0 1 40 2 ns tGRCAN1 data input to clock setup rising clk edge 3 ns tGRCAN2 data input from clock hold rising clk edge 3 ns 1 Guaranteed by design not tested 2 Verified by stati...

Page 458: ...gaisler GR740 40 Mechanical description 40 1 Component and package The device is available as CCGA625 and LGA625 Please refer to section 40 4 for the package draw ing A placement diagram is available...

Page 459: ...GR740 UM DS Nov 2017 Version 1 7 459 www cobham com gaisler GR740 40 2 Package placement diagram Figure 74 Placement top view through package Figure 75 Placement bottom view...

Page 460: ...SPI A12 SYS_CLK I LVCMOS 3 3 Sys spw CLK A13 MEM_EXTCLK I LVCMOS 3 3 Sys spw CLK A14 SYS_EXTLOCK I LVCMOS 3 3 Sys spw CLK A15 JTAG_TCK I LVCMOS 3 3 JTAG A16 JTAG_TRST I LVCMOS 3 3 Low JTAG A17 GPIO 1...

Page 461: ...0 IO LVCMOS 3 3 PROM C10 GR1553_BUSBTXIN O LVCMOS 3 3 High MIL 1553 C11 SPI_SCK IO LVCMOS 3 3 SPI C12 SPI_SEL I LVCMOS 3 3 Low SPI C13 SPI_SLVSEL 0 O LVCMOS 3 3 Low SPI C14 SPI_SLVSEL 1 O LVCMOS 3 3...

Page 462: ...G3V3 E4 PROMIO_ADDR 15 O LVCMOS 3 3 PROM E5 PROMIO_ADDR 13 O LVCMOS 3 3 PROM E6 PROMIO_ADDR 1 O LVCMOS 3 3 PROM E7 PROMIO_DATA 7 IO LVCMOS 3 3 PROM E8 PROMIO_DATA 1 IO LVCMOS 3 3 PROM E9 VDIG3V3 Power...

Page 463: ...High Bootstrap F21 VSS2V5 Power ground pin VSS2V5 F22 SPW_TXS_P 6 O LVDS 2 5 Pos SpaceWire F23 SPW_TXS_N 6 O LVDS 2 5 Neg SpaceWire F24 SPW_TXD_P 6 O LVDS 2 5 Pos SpaceWire F25 SPW_TXD_N 6 O LVDS 2 5...

Page 464: ...ound pin GND H14 VDD1V2 Power ground pin VDD H15 GND Power ground pin GND H16 VDD1V2 Power ground pin VDD H17 GND Power ground pin GND H18 VDD1V2 Power ground pin VDD H19 VSS3V3 Power ground pin VSS3V...

Page 465: ...ground pin VSS3V3 K8 VDD1V2 Power ground pin VDD K9 GND Power ground pin GND K10 VDD1V2 Power ground pin VDD K11 GND Power ground pin GND K12 VDD1V2 Power ground pin VDD K13 GND Power ground pin GND K...

Page 466: ...net M2 ETH0_GTXCLK I LVCMOS 3 3 Ethernet M3 ETH0_RXD 5 I LVCMOS 3 3 Ethernet M4 ETH0_RXD 3 I LVCMOS 3 3 Ethernet M5 ETH0_RXD 7 I LVCMOS 3 3 Ethernet M6 VDIG3V3 Power ground pin VDIG3V3 M7 VSS3V3 Power...

Page 467: ...RXS_P 3 I LVDS 2 5 DiffTerm Pos SpaceWire N23 SPW_RXS_N 3 I LVDS 2 5 DiffTerm Neg SpaceWire N24 SPW_RXD_P 3 I LVDS 2 5 DiffTerm Pos SpaceWire N25 SPW_RXD_N 3 I LVDS 2 5 DiffTerm Neg SpaceWire P1 ETH0_...

Page 468: ...ground pin VDD R16 GND Power ground pin GND R17 VDD1V2 Power ground pin VDD R18 GND Power ground pin GND R19 VDIG3V3 Power ground pin VDIG3V3 R20 VSS3V3 Power ground pin VSS3V3 R21 VDIG2V5 Power grou...

Page 469: ...ground pin VDD U10 GND Power ground pin GND U11 VDD1V2 Power ground pin VDD U12 GND Power ground pin GND U13 VDD1V2 Power ground pin VDD U14 GND Power ground pin GND U15 VDD1V2 Power ground pin VDD U...

Page 470: ...OS 3 3 SDRAM W5 MEM_DQ 12 IO LVCMOS 3 3 SDRAM W6 VSS3V3 Power ground pin VSS3V3 W7 VDIG3V3 Power ground pin VDIG3V3 W8 VSS3V3 Power ground pin VSS3V3 W9 VDIG3V3 Power ground pin VDIG3V3 W10 VSS3V3 Pow...

Page 471: ...ower ground pin VSS2V5 Y23 VSS2V5 Power ground pin VSS2V5 Y24 VSS2V5 Power ground pin VSS2V5 Y25 VSS2V5 Power ground pin VSS2V5 AA1 MEM_DQ 23 IO LVCMOS 3 3 SDRAM AA2 MEM_DQ 21 IO LVCMOS 3 3 SDRAM AA3...

Page 472: ...16 MEM_DQ 59 IO LVCMOS 3 3 SDRAM AB17 MEM_DQ 61 IO LVCMOS 3 3 SDRAM AB18 MEM_DQ 67 IO LVCMOS 3 3 SDRAM AB19 MEM_DQ 71 IO LVCMOS 3 3 SDRAM AB20 MEM_DQ 77 IO LVCMOS 3 3 SDRAM AB21 MEM_DQ 86 IO LVCMOS 3...

Page 473: ...LVCMOS 3 3 SDRAM AD10 MEM_ADDR 6 O LVCMOS 3 3 SDRAM AD11 MEM_ADDR 10 O LVCMOS 3 3 SDRAM AD12 MEM_ADDR 14 O LVCMOS 3 3 SDRAM AD13 MEM_RASN O LVCMOS 3 3 Low SDRAM AD14 MEM_DQ 50 IO LVCMOS 3 3 SDRAM AD15...

Page 474: ...EM_DQ 54 IO LVCMOS 3 3 SDRAM AE16 MEM_DQ 58 IO LVCMOS 3 3 SDRAM AE17 MEM_DQ 62 IO LVCMOS 3 3 SDRAM AE18 MEM_DQ 66 IO LVCMOS 3 3 SDRAM AE19 MEM_DQ 70 IO LVCMOS 3 3 SDRAM AE20 MEM_DQ 72 IO LVCMOS 3 3 SD...

Page 475: ...configurations depending on device type see ordering information in section 42 The drawing in section 40 4 2 applies to prototypes using the first version of the package package revision 0 Sections 40...

Page 476: ...GR740 UM DS Nov 2017 Version 1 7 476 www cobham com gaisler GR740 40 4 3 Package drawing for GR740 YY CP MP MSEQ MSEV MSQ MSV LG625...

Page 477: ...GR740 UM DS Nov 2017 Version 1 7 477 www cobham com gaisler GR740 40 4 4 Package drawing for GR740 YY CP MP MSEQ MSEV MSQ MSV CG625...

Page 478: ...GR740 UM DS Nov 2017 Version 1 7 478 www cobham com gaisler GR740...

Page 479: ...erature and thermal resistance Table 598 Temperature limits Parameter Symbol Min Max Unit Storage temperature Tstorage TBD TBD C Operating temperature Toperation 40 125 C Table 599 Thermal resistance...

Page 480: ...ineering model prototype 0 0 A GR740 YY LG625 Engineering model prototype 0 1 B GR740 YY CG625 Engineering model prototype 0 1 B GR740 CP LG625 Engineering model prototype 1 1 C D GR740 CP CG625 Engin...

Page 481: ...r AMBA ERROR Affected Not affected 6 Memory controller incompatibility in full width mode with UT8SD MQ64M48 Affected Not affected 7 Temperature sensor This issue depends on the package version used 8...

Page 482: ...che is enabled The DPBM function was added as a new feature to GR740 and not present in earlier LEON4 devices the workaround to turn this off reverts back to the previous behavior without any other si...

Page 483: ...e to This issue is only present in silicon revision 0 43 2 4 LEON4 partial WRPSR The LEON4 partial WRPSR is incorrectly implemented in silicon revision 0 Partial WRPSR may update the ICC and CWP field...

Page 484: ...e MMU is enabled The TLB is normally only dis abled for debugging purposes and operating systems keep the TLB enabled Applicable to This issue is only present in silicon revision 0 43 2 10 LEON4 break...

Page 485: ...Ethernet controllers in the design share the same MDIO bus If the Ethernet debug communica tions link EDCL is enabled then the Ethernet controller will try to configure the external transceiver after...

Page 486: ...EN and JTAG_TRST This is a safety precaution and board designers should still properly connect these sig nals to ground 43 2 20 Additional fields in register for bootstrap signals The external signals...

Page 487: ...12 8 us unless it receives an FCT i e unless enough space is freed up in the core s receive FIFOs With silicon revision 1 the core will not enter run state unless it has both received and transmitted...

Page 488: ...any responsibility or liability arising out of the application or use of any product or service described herein except as expressly agreed to in writing by Cobham nor does the purchase lease or use...

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