GR740-UM-DS, Nov 2017, Version 1.7
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GR740
15.7
PCI trace buffer
15.7.1 Trace data
The data from the trace buffer is accessible in the last 128 KiB block of the core’s AHB I/O area. Each
32-bit word in the first 64 KiB of this block represents a sample of the AD PCI signal. The second 64
KiB of the block is the corresponding PCI control signal. Each 32-bit word is defined in table 270.
15.7.2 Triggering function
The core can be programmed to trigger on any combination of the PCI AD and PCI Control signals by
setting up the desired pattern and mask in the PCI trace buffer registers accessible via the APB slave
interface. Each bit the PCI AD signal and any PCI control signal can be masked (mask bit equal to
zero) to always match the triggering condition.
The “Trig count” field in the “PCI trace buffer: counter & mode” register defines how many times the
trigger condition should occur before the trace buffer disarms and eventually stops sampling. The
number of samples stored after the triggering condition occurs is defined by the “Delayed stop“ field.
To start sampling, the trace buffer needs to be armed by writing one to the start bit in the “PCI trace
buffer: Control“ register. The state of the trace buffer can be determine by reading the Armed and
Enable/Running bit in the control register. When the Armed bit is set, the triggering condition has not
occurred. The Enable/Running bit indicates that the trace buffer still is storing new samples. When the
delayed stop field is set to a non zero value, the Enabled bit is not cleared until all samples are stored
in the buffer). The trace buffer can also be disarmed by writing the “stop” bit in the “PCI trace buffer:
control” register.
When the trace buffer has been disarmed, the “trig index” in the “PCI trace buffer: control” register is
updated with index of trace entry which match the triggering condition. The address offset of this
entry is the value of the “trig index“ field times 4.
15.7.3 Trace Buffer APB interface
A separate APB register is available on the Debug AHB bus for access of the PCI trace buffer. The
register layout is the same as for the core’s AHB interface but only registers related to the PCI trace
buffer are available. The trace buffer data is located at offset 0x20000 for PCI AD and offset 0x30000
for PCI control signals.
15.8
Interrupts
The core is capable of sampling the PCI INTA-D signals and forwarding the interrupt to the APB bus.
The “host INT mask” field in the control register is used to only sample the valid PCI INT signal(s).
Table 270.
GRPCI2 PCI control signal trace (32-bit word)
31
20 19
16 15 14 13 12 11 10
9
8
7
6
5
4
3
0
RESERVED
CBE[3:0]
F
R
A
M
E
I
R
D
Y
T
R
D
Y
S
T
O
P
D
E
V
S
E
L
P
A
R
P
E
R
R
S
E
R
R
I
D
S
E
L
R
E
Q
G
N
T
L
O
C
K
R
S
T
RES
31: 20
RESERVED
19: 3
The state of the PCI control signals.
2: 0
RESERVED
