GR740-UM-DS, Nov 2017, Version 1.7
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GR740
The control register field LB selects which AHB master interfaces that should be used when the core
fetches IOPTEs or APV bit vector data from memory (protection data structures described under sec-
tions 12.4 and 12.5).
12.2.3 AHB read transfers
When a read transfer is registered on the slave interface connected to the Master I/O AHB bus, the
core will insert wait states. The master interface then requests the bus and starts the read transfer on
the master side. Single transfers on the slave side are normally translated to single transfers with the
same AHB address and control signals on the master side.
If the transfer is a burst transfer to a prefetchable location, the master interface will prefetch data in
the internal read FIFO. If the burst on the slave side was an incremental burst of unspecified length
(INCR), the length of the burst is unknown. In this case the master interface performs an incremental
burst up to a 32-byte address boundary
.
When the burst transfer is completed on the master side, the
core will return data with zero wait states.
If the burst is to a non-prefetchable area, the burst transfer on the master side is performed using
sequence of NONSEQ, BUSY and SEQ transfers. The first access in the burst on the master side is of
NONSEQ type. Since the master interface can not decide whether the burst will continue on the slave
side or not, the system bus is held by performing BUSY transfers. On the slave side, the master that
initiated the transfer is allowed in bus arbitration. The first access in the transfer is completed by
returning read data. The next access in the transfer on the slave side is extended by asserting
HREADY low. On the master side the next access is started by performing a SEQ transfer (and then
holding the bus using BUSY transfers). This sequence is repeated until the transfer is ended on the
slave side.
In case of an ERROR response on the master side the ERROR response will be given for the same
access (address) on the slave side. SPLIT and RETRY responses on the master side are re-attempted
until an OKAY or ERROR response is received.
12.2.4 AHB write transfers
The core implements posted writes. During the AHB write transfer on the slave side the data is buff-
ered in the internal write FIFO and the transfer is completed on the slave side by always giving an
OKAY response. The master interface requests the bus and performs the write transfer when the mas-
ter bus is granted. If the burst transfer crosses the 32-byte write burst address boundary, a RETRY
response is given. When the core has written the contents of the FIFO out on the master side, the core
will allow the master on the slave side to perform the remaining accesses of the write burst transfer.
12.2.5 Read and write combining
Read and write combining allows the core to assemble or split AMBA accesses on the core’s slave
interface into one or several accesses on the master interface. The effects of read and write combining
is shown in the table below.
Table 115.
Read and write combining
Access on slave interface
Resulting access(es) on master interface
BYTE or HALF-WORD single read
access to any area
Single access of same size
BYTE or HALF-WORD read burst
to prefetchable area
Incremental read burst of same access size as on slave interface, the length is the
same as the number of 32-bit words in the read buffer, but will not cross the read
burst boundary.
BYTE or HALF-WORD read burst
to non-prefetchable area
Incremental read burst of same access size as on slave interface, the length is the
same as the length of the incoming burst. The master interface will insert BUSY
cycles between the sequential accesses.
