GR740-UM-DS, Nov 2017, Version 1.7
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If the bit at the selected position is ‘0’, the access to the page is allowed and the core will propagate
the access. If the selected bit is ‘1’, and the access is an read access, an AMBA ERROR response is
given to the master initiating the access. If the selected bit is ‘1’, and the access is a write access, the
write is inhibited (not propagated through the bridge).
12.4.1 Access Protection Vector cache
The core has internal memory that can cache the Access Protection Vector. The cache has 32 lines
where each line is 16 bytes. These parameters can be read via Capability registers 0 and 1. The RAMs
in the APV cache are shared with the IOMMU TLB.
The cache is implemented as a direct-mapped cache built up of one data RAM and one tag RAM. The
number of locations in each RAM is the number of lines in the cache. The width of the data RAM
(cache line size) is the same as the size of the AMBA accesses used to fetch the APV from main mem-
ory. The address used to select a position in the RAMs, called the set address, has
log2(number of
lines in the cache)
= 5 bits.
The core will only cache bit vector data for accesses to the memory area 0x00000000 - 0x7FFFFFFF
(SDRAM memory area). Capability register 1 contains an address and a mask that describes this area.
Bit vector data for the specified memory range will be cached by the core. Bit vector data for accesses
made outside the memory range will not be placed in the cache, and will instead be fetched for mem-
ory on each access.
The number of address bits taken from the physical address required to uniquely address one position
in the bit vector depends on the cache line size and the page size. The number of required bits is
shown in table 120 below.
As the cache is not large enough to hold a copy of each position in the bit vector, part of the physical
address and group will be placed in the cache tag RAM instead. The arrangement will be:
Since the physical address is used as the set address, accesses from a master assigned to one group
may evict cached bit vector data belonging to another group. This may not be wanted in systems
where interference between groups of masters should be minimized. In order to minimize inter-group
interference, the core can use the group ID in the set address, this functionality is called group-set-
addressing:
Table 120.
Cache line size vs. physical address bits
Cache line
size in bits
Bits of physical address needed to identify one position depending on page size
4 KiB
8 KiB
16 KiB 32 KiB 64 KiB 128 KiB
256 KiB
512 KiB
128
12
11
10
9
8
7
6
5
Table 121.
Set address/ TAG arrangement
Set address:
31
4
0
Not present
Low bits of physical
address
Contents of Tag RAM:
10
8
7
1
0
Not present
Group ID
High bits of physical address
V
0
Valid (V) - Signals that addressed position in cache contains valid data
