GR740-UM-DS, Nov 2017, Version 1.7
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GR740
loaded into the transmitter FIFO. When the FIFO is empty the TE bit is set in the status register. If the
transmitter is disabled, it will immediately stop any active transmissions including the character cur-
rently being shifted out from the transmitter shift register. The transmitter holding register may not be
loaded when the transmitter is disabled or when the FIFO is full. If this is done, data might be over-
written and one or more frames are lost.
The TF status bit (not to be confused with the TF control bit) is set if the transmitter FIFO is currently
full and the TH bit is set as long as the FIFO is
less
than half-full (less than half of entries in the FIFO
contain data). The TF control
bit enables FIFO interrupts when set. The status register also contains a
counter (TCNT) showing the current number of data entries in the FIFO.
When flow control is enabled, the CTSN input must be low in order for the character to be transmit-
ted. If it is deasserted in the middle of a transmission, the character in the shift register is transmitted
and the transmitter serial output then remains inactive until CTSN is asserted again. If the CTSN is
connected to a receivers RTSN, overrun can effectively be prevented.
23.2.2 Receiver operation
The receiver is enabled for data reception through the receiver enable (RE) bit in the UART control
register. The receiver looks for a high to low transition of a start bit on the receiver serial data input
pin. If a transition is detected, the state of the serial input is sampled a half bit clocks later. If the serial
input is sampled high the start bit is invalid and the search for a valid start bit continues. If the serial
input is still low, a valid start bit is assumed and the receiver continues to sample the serial input at
one bit time intervals (at the theoretical centre of the bit) until the proper number of data bits and the
parity bit have been assembled and one stop bit has been detected. The serial input is shifted through
an 8-bit shift register where all bits have to have the same value before the new value is taken into
account, effectively forming a low-pass filter with a cut-off frequency of 1/8 system clock.
The receiver also has a FIFO which is identical to the one in the transmitter.
During reception, the least significant bit is received first. The data is then transferred to the receiver
FIFO and the data ready (DR) bit is set in the UART status register as soon as the FIFO contains at
least one data frame. The parity, framing and overrun error bits are set at the received byte boundary,
at the same time as the receiver ready bit is set. The data frame is not stored in the FIFO if an error is
detected. Also, the new error status bits are or:ed with the old values before they are stored into the
status register. Thus, they are not cleared until written to with zeros from the AMBA APB bus. If both
the receiver FIFO and shift registers are full when a new start bit is detected, then the character held in
the receiver shift register will be lost and the overrun bit will be set in the UART status register. A
break received (BR) is indicated when a BREAK has been received, which is a framing error with all
data received being zero.
If flow control is enabled, then the RTSN will be negated (high) when a valid start bit is detected and
the receiver FIFO is full. When the holding register is read, the RTSN will automatically be reasserted
again.
The RF status bit (not to be confused with the RF control bit) is set when the receiver FIFO is full.
The RH status bit is set when the receiver FIFO is half-full (at least half of the entries in the FIFO con-
tain data frames). The RF control bit enables receiver FIFO interrupts when set. A RCNT field is also
available showing the current number of data frames in the FIFO.
23.3
Baud-rate generation
Each UART contains a 20-bit down-counting scaler to generate the desired baud-rate. The scaler is
clocked by the system clock and generates a UART tick each time it underflows. It is reloaded with
the value of the UART scaler reload register after each underflow. The resulting UART tick frequency
should be 8 times the desired baud-rate. If the EC bit is set, the ticks will be generated with the same
frequency as the external clock input instead of at the scaler underflow rate. In this case, the frequency
of external clock must be less than half the frequency of the system clock.
