GR740-UM-DS, Nov 2017, Version 1.7
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GR740
9.2.8
Scrubber
The cache is implemented with an internal memory scrubber to prevent build-up of errors in the cache
memories. The scrubber is controlled via two registers in the cache configuration interface. To scrub
one specific cache line the index and way of the line is set in the scrub control register. The scrub
operation is started by setting the the pending bit to 1. The scrubber can also be configured to contin-
uously loop through and scrub each cache line by setting the enabled bit to 1. In this mode, the delay
between the scrub operation on each cache line is determine by the scrub delay register (in clock
cycles).
9.2.9
Locked way
One or more ways can be configured to be locked (not replaced). The number of ways that should be
locked is configured by the locked-way field in the control register. The way to be locked is starting
with the uppermost way (for a 4-way associative cache way 4 is the first locked way, way 3 the sec-
ond, and so on). After a way is locked, the cache-way has to be flushed with the “way flush” function
to update the tag to match the desired locked address. During this “way flush” operation, the data can
also be fetched from memory.
9.3
Operation
9.3.1
Read
A cachable read access to the cache results in a tag lookup to determine if the requested data is located
in the cache memory. For a hit (requested data is in the cache) the data is read from the cache and no
read access is issued to the memory. If the requested data is not in the cache (cache miss), the cache
controller issues a read access to the memory controller to fetch the cache line containing the
requested data. The replacement policy determines which cache line in a multi-way configuration that
should be replaced and its tag is updated. If the replaced cache line is modified (dirty) this data is
stored in a write buffer and after the requested data is fetched from memory the replaced cache line is
written to memory.
For a non-cachable read access to the cache, the cache controller can issue a single read access or a
burst read access to fetch the data from memory. The access type is determine by how the cache is
configured regarding hprot support and bypass line fetch in the access control register. The data is
stored in a read buffer and the state of the cache is not modified in any way.
The cache will insert wait-states until the read access is determined to be a cache hit or miss. For a
cache hit the data is then delivered. For a miss the cache can insert wait-states during the memory
fetch or issue a AMBA SPLIT (depending on how the cache is configured).
9.3.2
Write
A cachable write access to the cache results in a tag lookup to determine if the cache line is present in
the cache. For a hit the cache line is updated. No access is issued to the memory for a copy-back con-
figuration. When the cache is configured as a write-through cache, each write access is also issued
towards memory. For a miss, the replacement policy determines which cache line in a multi-way con-
figuration that should be replaced and updates its tag. If the replaced cache line is dirty, it is stored in
a write buffer to be written back to the memory. The new cache line is updated with the data from the
write access and for a non-128-bit access the rest of the cache line is fetched from memory. Last the
replaced cache line is written to memory (when copy-back policy is used and the replaced cache line
was marked dirty). When the cache is configured as a write-through cache, no cache lines are marked
as dirty and no cache line needs to be written back to memory. Instead the write access is issued
towards the memory as well. A new cache line is allocated on a miss for a cacheable write access
independent of write policy (copy-back or write-through).
