GR740-UM-DS, Nov 2017, Version 1.7
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12.3.2 Delays incurred from access protection
The time required for the core’s master interface to start an access may be delayed by access protec-
tion checks. Table 118 below shows the added delays, please refer to section 12.2.6 for a description
of delays from the core’s bridge operation.
12.4
Access Protection Vector
The Access Protection Vector (APV) consists of a continuous bit vector where each bit determines the
access rights to a memory page. The bit vector provides access restriction on the full 4 GiB AMBA
address space. The required size of the bit vector depends on the page size used by the core, see table
below:
Each group can have a bit vector with a base address specified by a field in the group’s Group Control
Register. When a master performs an access to the core, the master’s group number is used to select
one of the available bit vectors. The AMBA access size used to fetch the vector is fixed to quad-word
(128-bits) and can be read out from the core’s Capability register 1. When the AMBA access size to
use is 128-bits and the page size is 4 KiB, bits 31:19 of the incoming address (HADDR) are used to
index a word in the bit vector, and bits HADDR[18:12] are used to select one of the 128 bits in the
fetched data. For each increase in page size one bit less of the physical address is used.
The lowest page is protected by the most significant bit in the bit vector. This means that page 0 is
protected by the most significant bit in byte 0 read from the bit vector’s base address (using big endian
addressing). When performing WORD accesses, the lowest page is protected by bit 31 in the accessed
word (using the bit numbering convention used throughout this document). When performing
4WORD (128-bit) accesses, the lowest page is protected by bit 127 in the accessed word. This allows
the same bit vector layout regardless of access size used by the IOMMU to fetch bit vector data.
Table 118.
Access protection check latencies
Protection mode
Delay in clock cycles on master side
Disabled
0
Write-protection only and read access
0
Master assigned to group in passthrough or inactive group
1
Access Protection Vector, cache hit
1
Access Protection Vector cache miss, cache disabled/not implemented
Minimum
x
4 clock cycles
IOMMU Protection, cache hit
1
IOMMU Protection, TLB miss, TLB disabled/not implemented
Minimum
x
4 clock cycles
x
The core may suffer additional AMBA bus delays when accessing the vector in memory. 4 cycles is the minimum time
required and assumes that the core is instantly granted access to the bus and that data is delivered with zero wait states.
Table 119.
Bit vector size vs. page size
Page size
Bit vector size
4 KiB
128 KiB
8 KiB
64 KiB
16 KiB
32 KiB
32 KiB
16 KiB
64 KiB
8 KiB
128 KiB
4 KiB
256 KiB
2 KiB
512 KiB
1 KiB
