GR740-UM-DS, Nov 2017, Version 1.7
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GR740
6.1.4
Memory management unit
Each processor core contains a SPARC V8 Reference Memory Management Unit (SRMMU). The
SRMMU implements the full SPARC V8 MMU specification, and provides mapping between multi-
ple 32-bit virtual address spaces and physical memory. A three-level hardware table-walk is imple-
mented, and the MMU has 16 instruction and 16 data fully associative TLB entries.
6.1.5
On-chip debug support
The LEON4 pipeline includes functionality to allow non-intrusive debugging on target hardware. To
aid software debugging, up to four watchpoint registers can be enabled. Each register can cause a
breakpoint trap on an arbitrary instruction or data address range. When the (optional) debug support
unit is attached, the watchpoints can be used to enter debug mode. Through a debug support interface,
full access to all processor registers and caches is provided. The debug interfaces also allows single
stepping, instruction tracing and hardware breakpoint/watchpoint control. An internal trace buffer can
monitor and store executed instructions, which can later be read out via the debug interface.
6.1.6
Interrupt interface
LEON4 supports the SPARC V8 interrupt model with a total of 15 asynchronous interrupts. The inter-
rupt interface provides functionality to both generate and acknowledge interrupts.
6.1.7
AMBA interface
The cache system implements an AMBA AHB master to load and store data to/from the caches. The
interface is compliant with the AMBA-2.0 standard. During line refill, incremental burst are gener-
ated to optimise the data transfer. The AMBA interface makes use of the full width of the 128-bit bus
on cache line fills. The processor also has a snoop AHB slave input port which is used to monitor the
accesses made by other masters on the processor AHB bus.
6.1.8
Power-down mode
The LEON4 processor core implements a power-down mode, which halts the pipeline and caches
until the next interrupt. The processor supports clock gating during the power down period by provid-
ing a clock-enable signal to the system’s clock gating unit. A small part of the processor is always
clocked, to check for wake-up conditions and maintain cache coherency.
6.1.9
Multi-processor support
LEON4 is designed to be used in multi-processor systems. Each processor has a unique index to allow
processor enumeration. The write-through caches and snooping mechanism guarantees memory
coherency in shared-memory systems.
