GR740-UM-DS, Nov 2017, Version 1.7
336
www.cobham.com/gaisler
GR740
24.3.6 Transmit register
Table 425.
0x30 - TX - Transmit register
24.3.7 Receive register
Table 426.
0x34 - RX - Receive register
24.3.8 Slave select register
Table 427.
0x38 - SLVSEL - Slave select register
31
0
TDATA
0
w
31: 0
Transmit data (TDATA) - Writing a word into this register places the word in the transmit queue.
This register will only react to writes if the Not full (NF) bit in the Event register is set. The layout of
this register depends on the value of the REV field in the Mode register:
Rev = ‘0’: The word to transmit should be written with its least significant bit at bit 0.
Rev = ‘1’: The word to transmit should be written with its most significant bit at bit 31.
31
0
RDATA
0
r
31: 0
Receive data (RDATA) - This register contains valid receive data when the Not empty (NE) bit of the
Event register is set. The placement of the received word depends on the Mode register fields LEN
and REV:
For LEN = 0b0000 - The data is placed with its MSb in bit 31 and its LSb in bit 0.
For other lengths and REV = ‘0’ - The data is placed with its MSB in bit 15.
For other lengths and REV = ‘1’ - The data is placed with its LSB in bit 16.
To illustrate this, a transfer of a word with eight bits (LEN = 7) that are all set to one will have the
following placement:
REV = ‘0’ - 0x0000FF00
REV = ‘1’ - 0x00FF0000
31
2
1
0
RESERVED
SLVSEL
0
0b11
r
rw
31: 2
RESERVED
1: 0
Slave select (SLVSEL) - The core’s slave select signals are mapped to this register on bits 1:0. Soft-
ware is responsible for activating the correct slave select signals.
