GR740-UM-DS, Nov 2017, Version 1.7
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GR740
15.4
PCI Initiator interface
The PCI master interface is accessible via the AMBA AHB slave interface. The AHB slave interface
occupies 1 GiB of the AHB memory address space and 256 KiB of AHB I/O address space. An access
to the AHB memory address area is translated to a PCI memory cycle. An access to the first 64 KiB of
the AHB IO area is translated to a PCI I/O cycle. The next 64 KiB are translated to PCI configuration
cycles. A PCI trace buffer is accessible via the last 128 KiB of the AHB I/O area.
15.4.1 Memory cycles
A single read access to the AHB memory area is translated into a PCI memory read access, while a
burst read translates into a PCI memory read multiple access. A write to this memory area is translated
into a PCI write access.
The address translation is determined by AHB master to PCI address mapping registers accessible via
the APB slave interface. Each AHB master on the AMBA AHB bus has its own mapping register.
These registers contain the MSbs of the PCI address.
When the PCI master is busy performing a transaction on the PCI bus and not able to accept new
requests, the AHB slave interface will respond with an AMBA RETRY response. This occurs on
reads when the PCI master is fetching the requested data to fill the read FIFO or on writes when no
write FIFO is available.
15.4.2 I/O cycles
Accesses to the low 64 KiB of the AHB I/O address area are translated into PCI I/O cycles. The
address translation is determined by the “AHB to PCI mapping register for PCI I/O”. This register sets
the 16 MSb of the PCI address. The “AHB to PCI mapping register for PCI I/O” is accessible via the
APB slave interface. When the “IB” (PCI IO burst) bit in the Control register (accessible via the APB
slave interface) is cleared, the PCI master does not perform burst I/O accesses.
15.4.3 Configuration cycles
Accesses to the second 64 KiB address block (address offset range 64 KiB to 128 KiB) of the AHB I/
O area are translated into PCI configuration cycles. The AHB address is translated into PCI configura-
tion address differently for type 0 and type 1 PCI configuration cycles. When the “bus number” field
in the control register (accessible via the APB slave interface) is zero, type 0 PCI configuration cycles
are issued. When the “bus number“ field is non-zero, type 1 PCI configuration cycles are issued to the
PCI bus determined by this field. The AHB I/O address mapping to PCI configuration address for
type 0 and type 1 PCI configuration cycles is defined in table 264 and table 265.
Only the system host is allowed to generate PCI configuration cycles. The core provides a system host
input signal that must be asserted (active low) for PCI system host operations. The status of this signal
is available in the Status & Capability register accessible via the APB slave interface.When the “CB”
(PCI Configuration burst) bit in the Control register (accessible via the APB slave interface) is
cleared, the PCI master does not perform burst configuration accesses.
Table 264.
GRPCI2 Mapping of AHB I/O address to PCI configuration cycle, type 0
31
16 15
11 10
8
7
2
1
0
AHB ADDRESS MSB
IDSEL
FUNC
REGISTER
BYTE
31: 16
AHB address MSbs: Not used for PCI configuration cycle address mapping.
15: 11
IDSEL: This field is decoded to drive PCI AD[IDSEL+10]. Each of the signals AD[31:11] are sup-
pose to be connected (by the PCI back plane) to one corresponding IDSEL line.
10: 8
FUNC: Selects function on a multi-function device.
