GR740-UM-DS, Nov 2017, Version 1.7
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GR740
6.9.7
ASI 0x19 - MMU registers
This ASI provides access to the MMU:s control and status registers. The following MMU registers
are implemented:
6.9.8
ASI 0x1C - MMU and cache bypass
Performing an access via ASI 0x1C will act as if MMU and cache were disabled. The address will not
be translated and the cache will not be used or updated by the access.
6.9.9
ASI 0x1E - MMU snoop tags diagnostic access
If the MMU has been configured to use separate snoop tags, they can be accessed via ASI 0x1E. This
is primarily useful for RAM testing, and should not be performed during normal operation. This ASI
is addressed the same way as the regular diagnostic ASI:s 0xC, 0xE, and the read/written data has the
layout as shown below:
[31:10] Address tag. The physical address tag of the cache line.
[1]:
Parity. The odd parity over the data tag. Only used when processor is implemented with fault-tolerance features.
[0]:
Invalid. When set, the cache line is not valid and will cause a cache miss if accessed by the processor. Only present
if fast snooping is enabled.
Table 45.
MMU registers (ASI = 0x19)
Address
Register
0x000
MMU control register
0x100
Context pointer register
0x200
Context register
0x300
Fault status register
0x400
Fault address register
Figure 6.
Snoop cache tag layout
0
11
2
1
12
31
ATAG
PAR
IV
“0000”
