GR740-UM-DS, Nov 2017, Version 1.7
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GR740
15.4.4 Error handling
When a read access issued by the PCI master is terminated with target-abort or master-abort, the AHB
slave generates an AMBA ERROR response when the “ER” bit in the control register is set. When the
“EI“ bit in the control register is set, an AMBA interrupt is generated for the error. The interrupt status
field in the control register indicates the cause of the error. See also the AMBA ERROR propagation
description in section 5.10.
15.5
PCI Target interface
The PCI Target occupies memory areas in the PCI address space corresponding to the BAR registers
in the PCI Configuration Space. Each BAR register (BAR0 to BAR2) defines the address allocation in
the PCI address space. The size of each BAR is set by the “BAR size and prefetch” registers accessi-
ble via the core specific Extended PCI Configuration Space. The size of a BAR can be determined by
checking the number of implemented bits in the BAR register. Non-implemented bits returns zero and
are read only.
This implementation has three PCI BARs. BAR0 and BAR1 default to prefetchable 128 MiB BARs
and BAR2 defaults to a non-prefetchable 8 MiB BAR.
15.5.1 Supported PCI commands
These are the PCI commands that are supported by the PCI target.
•
PCI Configuration Read/Write:
Burst and single access to the PCI Configuration Space. These
accesses are not transferred to the AMBA AHB bus except for the access of the user defined
capability list item in the Extended PCI Configuration Space.
•
Memory Read:
A read command to the PCI memory BAR is transferred to a single read access
on the AMBA AHB bus.
•
Memory Read Multiple, Memory Read Line:
A read multiple command to the PCI memory
BAR is transferred to a burst access on the AMBA AHB bus. This burst access prefetch data to
fill the maximum amount of data that can be stored in the FIFO.
•
Memory Write, Memory Write and Invalidate:
These command are handled similarly and are
transferred to the AMBA AHB bus as a single or burst access depending on the length of the PCI
access (a single or burst access).
7: 2
REGISTER: Used to index a PCI DWORD in configuration space.
1: 0
BYTE: Used to set the CBE correctly for non PCI DWORD accesses.
Table 265.
GRPCI2 Mapping of AHB I/O address to PCI configuration cycle, type 1
31
16 15
11 10
8
7
2
1
0
AHB ADDRESS MSB
DEVICE
FUNC
REGISTER
BYTE
31: 16
AHB address MSbs: Not used for PCI configuration cycle address mapping.
15: 11
DEVICE: Selects which device on the bus to access.
10: 8
FUNC: Selects function on a multi-function device.
7: 2
REGISTER: Used to index a PCI DWORD in configuration space.
1: 0
BYTE: Used to set the CBE correctly for non PCI DWORD accesses.
Table 264.
GRPCI2 Mapping of AHB I/O address to PCI configuration cycle, type 0
