GR740-UM-DS, Nov 2017, Version 1.7
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GR740
43.2.24 SpaceWire router AMBA configuration port interrupt
Silicon revision 1 adds AMBA interrupt functionality to the SpaceWire router AMBA configuration
port so that AMBA interrupt line 31 can be asserted for events that can only generate SpaceWire inter-
rupt codes in silicon revision 0. See sections 2.4 and table 193.
43.2.25 SpaceWire: FCT must be sent before entering run-state
The SpaceWire port transmitter modules have been modified in silicon revision 1. The only scenario
when this modification will cause a different behavior is when the receive FIFOs are full when the
link state machine enters the connecting state.
With the silicon revision 0, the ports could enter run-state with full receive FIFOs, i.e without sending
an FCT. The other end of the link will wait for and FCT in the connecting state for 12.8 us. During this
period there is a risk that a packet transfer starts (since the link is in run-state). This packet will then
be discarded at the other end of the link, since that end receives an n-char before an FCT, and the link
will be disconnected. If the controller does not try to start a packet transfer, the other end of the link
will disconnect after 12.8 us unless it receives an FCT (i.e unless enough space is freed up in the
core's receive FIFOs).
With silicon revision 1, the core will not enter run-state unless it has both received and transmitted an
FCT, i.e if the receive FIFOs are full then none of the ends of the link enters run-state, and the other
end of the link will disconnect from the connecting state after 12.8 us.
The change applies to both the SpaceWire router’s external ports and to the Debug AHB bus Space-
Wire controller.
43.2.26 SpaceWire TDP: Extend functionality
The SpaceWire TDP controller has been extended for silicon revision 1. The new features are:
1.) Added support for 64 Distributed interrupts
2.) Increment time using External enable signal
3.) Load Time using External enable signal
4.) Logic to detect Missing SpacWire Time-code
5.) Latency corrected status can be write cleared
6.) Added additional option to synchronize time, using only SpW time-codes it is possible to
synchronize time.
The TDP controller has also been directly connected to the GPIO port. See sections 3.1 and 31.
43.2.27 GRFPU Floating Point Controller: Missing FDIV/FSQRT result
Workaround:
See GRLIB-TN-0013.
Applicable to:
This limitation is only present in silicon revision 0.
