GR740-UM-DS, Nov 2017, Version 1.7
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GR740
6.2.15 Address space identifiers (ASI)
In addition to the address, a SPARC processor also generates an 8-bit address space identifier (ASI),
providing up to 256 separate, 32-bit address spaces. During normal operation, the LEON4 processor
accesses instructions and data using ASI 0x8 - 0xB as defined in the SPARC standard. Using the
LDA/STA instructions, alternative address spaces can be accessed. The different available ASIs are
described in section 6.9.
6.2.16 Partial WRPSR
Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR instructions to only affect
the %PSR.ET field. If the WRPSR instruction’s rd field is non-zero, then the WRPSR write will only
update ET.
Partial WRPSR should only be used on silicon revision 1 of the GR740 device, see section 43.2.4.
6.2.17 Power-down
The processor has a power-down feature to minimize power consumption during idle periods. The
power-down mode is entered by performing a WRASR instruction to %asr19:
wr %g0, %asr19
During power-down, the pipeline is halted until the next interrupt occurs. Signals inside the processor
pipeline and caches are then static, reducing power consumption from dynamic switching. The default
setting of the clock-gating unit is to also disable the processor and FPU clock when the processor
enters this idle mode
Note: %asr19 must always be written with the data value zero to ensure compatiblity with future
extensions.
Note: This instruction must be performed in supervisor mode with interrupts enabled.
When resuming from power-down, the pipeline will be re-filled from the point of power-down and the
first instruction following the WRASR instruction will be executed prior to taking the interrupt trap.
Up to six instructions after the WRASR instruction will be fetched (possibly with cache miss if they
are not in cache) prior to fetching the trap handler.
6.2.18 Processor reset operation
The following table indicates the reset values of the registers which are affected by system reset. See
also reset values specified for other registers, such as the cache control register in sections 6.9 and
6.10. All other registers maintain their value or are undefined.
By default, the execution will start from address 0xC0000000. This can be overridden by setting the
reset start address register on the interrupt controller.
6.2.19 Multi-processor systems
The LEON4 processor supports symmetric multi-processing (SMP) and asymmetric multi-processing
(ASMP) configurations. The ID of the processor on which the code is executing can be read out by
reading the index field of the LEON4 configuration register.
Table 38.
Processor reset values
Register
Reset value
Trap Base Register
Trap Base Address field reset to 0xC0000000
PC (program counter)
0xC0000000
nPC (next program counter)
0xC0000004
PSR (processor status register)
ET=0, S=1
