16
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Contents
USBRXCSRH[15])
.............................................................................................
18.5.39
USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[15])
........
18.5.40
USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[15])
...
18.5.41
USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[15])
.
18.5.42
USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[15])
...
18.5.43
USB Host Receive Polling Interval Endpoint n Register
(USBRXINTERVAL[1]USBRXINTERVAL[15])
..............................................................
18.5.44
USB Request Packet Count in Block Transfer Endpoint n Registers
(USBRQPKTCOUNT[1]USBRQPKTCOUNT[15])
..........................................................
18.5.45
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
.....
18.5.46
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
....
18.5.47
USB External Power Control Register (USBEPC), offset 0x400
......................................
18.5.48
USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
........
18.5.49
USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
.................
18.5.50
USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
.
18.5.51
USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
.................
18.5.52
USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
....................
18.5.53
USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
...........
18.5.54
USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
....................
18.5.55
USB VBUS Droop Control Register (USBVDC), offset 0x430
.........................................
18.5.56
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCRIS), offset 0x434
...........
18.5.57
USB VBUS Droop Control Interrupt Mask Register (USBVDCIM), offset 0x438
....................
18.5.58
USB VBUS Droop Control Interrupt Status and Clear Register (USBVDCISC), offset 0x43C
....
18.5.59
USB ID Valid Detect Raw Interrupt Status Register (USBIDVRIS), offset 0x444
...................
18.5.60
USB ID Valid Detect Interrupt Mask Register (USBIDVIM), offset 0x448
............................
18.5.61
USB ID Valid Detect Interrupt Status and Clear Register (USBIDVISC), offset 0x44C
............
18.5.62
USB DMA Select Register (USBDMASEL), offset 0x450
..............................................
19
M3 Ethernet Media Access Controller (EMAC)
....................................................................
19.1
Introduction
...............................................................................................................
19.2
EMAC Block Diagram
...................................................................................................
19.3
Functional Description
..................................................................................................
19.3.1
MAC Operation
................................................................................................
19.3.2
Internal MII Operation
........................................................................................
19.3.3
Interrupts
.......................................................................................................
19.3.4
DMA Operation
................................................................................................
19.4
Initialization and Configuration
.........................................................................................
19.4.1
Software Configuration
.......................................................................................
19.5
Register Map
.............................................................................................................
19.6
Ethernet MAC Register Descriptions
.................................................................................
19.6.1
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register, offset 0x000
..
19.6.2
Ethernet MAC Interrupt Mask (MACIM) Register, offset 0x004
.........................................
19.6.3
Ethernet MAC Receive Control (MACRCTL) Register, offset 0x008
...................................
19.6.4
Ethernet MAC Transmit Control (MACTCTL) Register, offset 0x00C
..................................
19.6.5
Ethernet MAC Data (MACDATA) Register, offset 0x010
................................................
19.6.6
Ethernet MAC Individual Address 0 (MACIA0) Register, offset 0x014
.................................
19.6.7
Ethernet MAC Individual Address 1 (MACIA1) Register, offset 0x018
.................................
19.6.8
Ethernet MAC Threshold (MACTHR) Register, offset 0x01C
...........................................
19.6.9
Ethernet MAC Management Control (MACMCTL) Register, offset 0x020
.............................
19.6.10
Ethernet MAC Management Divider (MACMDV) Register, offset 0x024
.............................
19.6.11
Ethernet MAC Management Address Register (MACMAR), offset 0x028
...........................
19.6.12
Ethernet MAC Management Transmit Data (MACMTXD) Register, offset 0x02C
..................
19.6.13
Ethernet MAC Management Receive Data (MACMRXD) Register, offset 0x030
...................
19.6.14
Ethernet MAC Number of Packets (MACNP) Register, offset 0x034
.................................
19.6.15
Ethernet MAC Transmission Request (MACTR) Register, offset 0x038
.............................