Registers
737
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Enhanced Pulse Width Modulator (ePWM) Module
Table 7-32. Time-Base Control Register (TBCTL) Field Descriptions (continued)
Bit
Field
Value
Description
3
PRDLD
Active Period Register Load From Shadow Register Select
0
The period register (TBPRD) is loaded from its shadow register when the time-base counter,
TBCTR, is equal to zero.
A write or read to the TBPRD register accesses the shadow register.
1
The period register (TBPRD) is loaded from its shadow register when the time-base counter
TBCTR, is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit.
A write/read to the TBPRD register accesses the shadow register.
2
PHSEN
Counter Register Load From Phase Register Enable
0
Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS).
1
Allow Counter to be loaded from the Phase register (TBPHS) and shadow to active load events
when an EPWMxSYNCI input signal occurs or a software-forced sync signal, see bit 6.
1-0
CTRMODE
Counter Mode
The time-base counter mode is normally configured once and not changed during normal operation.
If you change the mode of the counter, the change will take effect at the next TBCLK edge and the
current counter value shall increment or decrement from the value before the mode change.
These bits set the time-base counter mode of operation as follows:
00
Up-count mode
01
Down-count mode
10
Up-down-count mode
11
Stop-freeze counter operation (default on reset)